| /external/clang/test/CodeGen/ |
| arm64_vrecps.c | 8 // vrecpss_f32 -> FRECPS Sd,Sa,Sb
14 // CHECK: frecps s0, s0, s1
18 // vrecpsd_f64 -> FRECPS Dd,Da,Db
24 // CHECK: frecps d0, d0, d1
|
| aarch64-neon-intrinsics.c | 879 // CHECK: frecps {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
885 // CHECK: frecps {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
891 // CHECK: frecps {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
[all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-frsqrt-frecp.s | 19 frecps v31.4s, v29.4s, v28.4s
20 frecps v3.2s, v8.2s, v12.2s
21 frecps v17.2d, v15.2d, v13.2d
23 // CHECK: frecps v31.4s, v29.4s, v28.4s // encoding: [0xbf,0xff,0x3c,0x4e]
24 // CHECK: frecps v3.2s, v8.2s, v12.2s // encoding: [0x03,0xfd,0x2c,0x0e]
25 // CHECK: frecps v17.2d, v15.2d, v13.2d // encoding: [0xf1,0xfd,0x6d,0x4e]
|
| neon-scalar-recip.s | 9 frecps s21, s16, s13
10 frecps d22, d30, d21
12 // CHECK: frecps s21, s16, s13 // encoding: [0x15,0xfe,0x2d,0x5e]
13 // CHECK: frecps d22, d30, d21 // encoding: [0xd6,0xff,0x75,0x5e]
|
| neon-diagnostics.s | 382 frecps v0.4s, v1.2d, v2.4s
383 frecps v0.8h, v1.8h, v2.8h
386 // CHECK-ERROR: frecps v0.4s, v1.2d, v2.4s
389 // CHECK-ERROR: frecps v0.8h, v1.8h, v2.8h
[all...] |
| arm64-advsimd.s | 331 frecps.2s v0, v0, v0
402 ; CHECK: frecps.2s v0, v0, v0 ; encoding: [0x00,0xfc,0x20,0x0e]
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vsqrt.ll | 5 ;CHECK: frecps.2s
8 %tmp3 = call <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
14 ;CHECK: frecps.4s
17 %tmp3 = call <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
23 ;CHECK: frecps.2d
26 %tmp3 = call <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
30 declare <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float>, <2 x float>) nounwind readnone
31 declare <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
32 declare <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double>, <2 x double>) nounwind readnone
|
| /frameworks/rs/driver/runtime/arch/ |
| asimd.ll | 40 declare <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float>, <2 x float>) nounwind readnone
41 declare <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
[all...] |
| /external/vixl/src/vixl/a64/ |
| logic-a64.cc | 3910 LogicVRegister Simulator::frecps(VectorFormat vform, function in class:vixl::Simulator
3925 LogicVRegister Simulator::frecps(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| disasm-a64.cc | [all...] |
| macro-assembler-a64.h | [all...] |
| simulator-a64.h | [all...] |
| simulator-a64.cc | [all...] |
| assembler-a64.h | [all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | 496 #include "traces/a64/sim-frecps-2d-trace-a64.h"
497 #include "traces/a64/sim-frecps-2s-trace-a64.h"
498 #include "traces/a64/sim-frecps-4s-trace-a64.h"
499 #include "traces/a64/sim-frecps-d-trace-a64.h"
500 #include "traces/a64/sim-frecps-s-trace-a64.h"
[all...] |
| test-simulator-a64.cc | [all...] |
| test-disasm-a64.cc | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| fp_and_simd.stdout.exp | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/clang/include/clang/Basic/ |
| arm_neon.td | [all...] |
| /external/valgrind/VEX/priv/ |
| host_arm64_defs.c | 695 case ARM64vecb_FRECPS64x2: *nm = "frecps"; *ar = "2d"; return;
696 case ARM64vecb_FRECPS32x4: *nm = "frecps"; *ar = "4s"; return;
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.td | [all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | 314 # CHECK: frecps.2s v0, v0, v0
[all...] |
| neon-instructions.txt | 177 # CHECK: frecps v5.4s, v7.4s, v16.4s
[all...] |
