| /external/llvm/test/CodeGen/AArch64/ |
| bitfield-insert-0.ll | 3 ; The encoding of lsb -> immr in the CGed bitfield instructions was wrong at one
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-basic-a64-undefined.txt | 20 # UBFM is undefined when s == 0 and imms<5> or immr<5> is 1.
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 212 /// the form N:immr:imms.
251 // Encode in Immr the number of RORs it would take to get *from* 0^m 1^n
255 unsigned Immr = (Size - I) & (Size - 1);
268 Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f);
290 /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
293 // Extract the N, imms, and immr fields.
295 unsigned immr = (val >> 6) & 0x3f; local
302 unsigned R = immr & (size - 1);
318 /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits
[all...] |
| /external/v8/src/arm64/ |
| assembler-arm64-inl.h | 1075 Instr Assembler::ImmR(unsigned immr, unsigned reg_size) {
1076 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
1077 ((reg_size == kWRegSizeInBits) && is_uint5(immr)));
1079 DCHECK(is_uint6(immr));
1080 return immr << ImmR_offset;
1093 Instr Assembler::ImmRotate(unsigned immr, unsigned reg_size) {
1095 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
1096 ((reg_size == kWRegSizeInBits) && is_uint5(immr)));
1098 return immr << ImmRotate_offset
[all...] |
| instructions-arm64.cc | 103 // N imms immr size S R
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| assembler-arm64.cc | [all...] |
| assembler-arm64.h | [all...] |
| disasm-arm64.cc | 425 unsigned r = instr->ImmR();
[all...] |
| constants-arm64.h | 162 V_(ImmR, 21, 16, Bits) \
[all...] |
| /external/valgrind/VEX/priv/ |
| host_mips_defs.c | 683 const HChar *showMIPSAluOp(MIPSAluOp op, Bool immR)
688 ret = immR ? "addiu" : "addu";
694 ret = immR ? "andi" : "and";
697 ret = immR ? "ori" : "or";
700 vassert(immR == False); /*there's no nor with an immediate operand!? */
704 ret = immR ? "xori" : "xor";
707 ret = immR ? "daddi" : "dadd";
710 ret = immR ? "dsubi" : "dsub";
713 ret = immR ? "slti" : "slt";
722 const HChar *showMIPSShftOp(MIPSShftOp op, Bool immR, Bool sz32
[all...] |
| host_tilegx_defs.c | [all...] |
| host_ppc_defs.c | 506 const HChar* showPPCAluOp ( PPCAluOp op, Bool immR ) {
508 case Palu_ADD: return immR ? "addi" : "add";
509 case Palu_SUB: return immR ? "subi" : "sub";
510 case Palu_AND: return immR ? "andi." : "and";
511 case Palu_OR: return immR ? "ori" : "or";
512 case Palu_XOR: return immR ? "xori" : "xor";
517 const HChar* showPPCShftOp ( PPCShftOp op, Bool immR, Bool sz32 ) {
519 case Pshft_SHL: return sz32 ? (immR ? "slwi" : "slw") :
520 (immR ? "sldi" : "sld");
521 case Pshft_SHR: return sz32 ? (immR ? "srwi" : "srw")
[all...] |
| host_arm64_defs.h | 193 UChar immR; /* 0 .. 63 */
203 extern ARM64RIL* ARM64RIL_I13 ( UChar bitN, UChar immR, UChar immS );
[all...] |
| guest_arm64_toIR.c | [all...] |
| host_arm64_defs.c | 362 ARM64RIL* ARM64RIL_I13 ( UChar bitN, UChar immR, UChar immS ) {
366 riL->ARM64riL.I13.immR = immR;
369 vassert(immR < 64);
385 (UInt)riL->ARM64riL.I13.immR,
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 112 int64_t immr = Op2.getImm(); local
114 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
118 ((imms + 1 == immr))) {
123 shift = immr;
126 shift = immr;
129 shift = immr;
132 shift = immr;
162 int ImmR = MI->getOperand(3).getImm();
166 if (ImmS < ImmR) {
168 int LSB = (BitWidth - ImmR) % BitWidth
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| Arm64Assembler.h | 236 uint32_t immr, uint32_t imms);
238 uint32_t immr, uint32_t imms);
240 uint32_t immr, uint32_t imms);
|
| Arm64Assembler.cpp | [all...] |
| /external/vixl/src/vixl/a64/ |
| assembler-a64.h | [all...] |
| instructions-a64.cc | 141 // N imms immr size S R
|
| macro-assembler-a64.h | [all...] |
| assembler-a64.cc | 1057 unsigned immr,
1062 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
1068 unsigned immr,
1073 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
1079 unsigned immr,
1084 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | [all...] |
| /art/compiler/dex/quick/arm64/ |
| arm64_lir.h | 237 kA64Asr3rrd, // asr [0001001100] immr[21-16] imms[15-10] rn[9-5] rd[4-0].
|
| target_arm64.cc | 292 // N imms immr size S R
|
