| /external/valgrind/none/tests/arm64/ |
| integer.stdout.exp | 2 add x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000
3 add w3, w4, w5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000
4 adc x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000
5 adc x3, x4, x5 :: rd 0000000000004abf rm 0000000000003039, rn 0000000000001a85, cin 1, nzcv 20000000 C
6 adc x3, x4, x5 :: rd ffffffffffffffff rm 0000000000000000, rn ffffffffffffffff, cin 0, nzcv 00000000
7 adc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn ffffffffffffffff, cin 1, nzcv 20000000 C
8 adc x3, x4, x5 :: rd 5859704f00000000 rm 3141592700000000, rn 2718172800000000, cin 0, nzcv 00000000
9 adc x3, x4, x5 :: rd 5859704f00000001 rm 3141592700000000, rn 2718172800000000, cin 1, nzcv 20000000 C
10 adc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 00000000
11 adc x3, x4, x5 :: rd 0000000000000001 rm 0000000000000000, rn 0000000000000000, cin 1, nzcv 20000000 C
[all...] |
| fp_and_simd.c | 1103 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1106 "mrs x9, nzcv; str x9, [%0, 48]; " \
[all...] |
| memory.stdout.exp | 2 LDR,STR (immediate, uimm12) (STR cases are MISSING)ldr x21, [x22, #24] :: rd 8f8e8d8c8b8a8988 rn (hidden), cin 0, nzcv 00000000
3 ldr w21, [x22, #20] :: rd 0000000087868584 rn (hidden), cin 0, nzcv 00000000
4 ldrh w21, [x22, #44] :: rd 0000000000009d9c rn (hidden), cin 0, nzcv 00000000
5 ldrb w21, [x22, #56] :: rd 00000000000000a8 rn (hidden), cin 0, nzcv 00000000
7 ldr x21, [x22], #-24 :: rd f7f6f5f4f3f2f1f0 rn (hidden), cin 0, nzcv 00000000
8 ldr x21, [x22, #-40]! :: rd cfcecdcccbcac9c8 rn (hidden), cin 0, nzcv 00000000
9 ldr x21, [x22, #-48] :: rd c7c6c5c4c3c2c1c0 rn (hidden), cin 0, nzcv 00000000
11 ldp x21, x28, [x22], #-24 ; add x21,x21,x28 :: rd f7f5f3f1efedebe8 rn (hidden), cin 0, nzcv 00000000
12 ldp x21, x28, [x22], #-24 ; eor x21,x21,x28 :: rd 0808080808080808 rn (hidden), cin 0, nzcv 00000000
13 ldp x21, x28, [x22, #-40]! ; add x21,x21,x28 :: rd a7a5a3a19f9d9b98 rn (hidden), cin 0, nzcv 00000000
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| nzcv-save.ll | 3 ; CHECK: mrs [[NZCV_SAVE:x[0-9]+]], NZCV
4 ; CHECK: msr NZCV, [[NZCV_SAVE]]
|
| arm64-regress-f128csel-flags.ll | 3 ; We used to not mark NZCV as being used in the continuation basic-block
21 ; function call since bl may corrupt NZCV. We were doing the right thing anyway,
|
| regress-f128csel-flags.ll | 3 ; We used to not mark NZCV as being used in the continuation basic-block
21 ; function call since bl may corrupt NZCV. We were doing the right thing anyway,
|
| regress-fp128-livein.ll | 3 ; Regression test for NZCV reg live-in not being added to fp128csel IfTrue BB,
|
| flags-multiuse.ll | 26 ; acceptable, but assuming the call preserves NZCV is not.
|
| /external/valgrind/none/tests/arm/ |
| v6intThumb.stdout.exp | 350 uxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
351 uxtb r1, r2 :: rd 0x00000097 rm 0x31415997, c:v-in 3, cpsr 0xf0000000 NZCV
359 sxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
360 sxtb r1, r2 :: rd 0xffffff97 rm 0x31415997, c:v-in 3, cpsr 0xf0000000 NZCV
368 uxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
369 uxth r1, r2 :: rd 0x00009597 rm 0x31419597, c:v-in 3, cpsr 0xf0000000 NZCV
377 sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
378 sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 3, cpsr 0xf0000000 NZCV
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ConditionalCompares.cpp | 66 STATISTIC(NumMultNZCVUses, "Number of ccmps rejected (NZCV used)");
67 STATISTIC(NumUnknNZCVDefs, "Number of ccmps rejected (NZCV def unknown)");
102 // operand that specifies the NZCV flag values when the condition is false and
125 // ccmp w1, #17, 4, ne ; 4 = nZcv
303 if (!I->readsRegister(AArch64::NZCV)) {
354 MIOperands(I).analyzePhysReg(AArch64::NZCV, TRI);
382 // Reject any live-in physregs. It's probably NZCV/EFLAGS, and very hard to
425 if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) {
646 // The NZCV immediate operand should provide flags for the case where Head
649 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(CmpBBTailCC)
[all...] |
| AArch64InstrInfo.cpp | 320 // if NZCV is used, do not fold.
321 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
347 // if NZCV is used, do not fold.
348 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
668 // Replace SUBSWrr with SUBWrr if NZCV is not used.
808 // Check that NZCV isn't set on the trace.
812 if (Instr.modifiesRegister(AArch64::NZCV, TRI) ||
813 (!CheckOnlyCCWrites && Instr.readsRegister(AArch64::NZCV, TRI)))
814 // This instruction modifies or uses NZCV after the one we want to
830 // Replace SUBSWrr with SUBWrr if NZCV is not used
[all...] |
| /external/v8/test/cctest/ |
| test-disasm-arm64.cc | [all...] |
| test-assembler-arm64.cc | 181 __ Msr(NZCV, xzr); \
[all...] |
| /external/v8/src/arm64/ |
| simulator-arm64.cc | 86 case NZCV:
399 nzcv_ = SimSystemRegister::DefaultValueFor(NZCV);
863 nzcv().SetN(N);
864 nzcv().SetZ(Z);
865 nzcv().SetC(C);
866 nzcv().SetV(V);
867 LogSystemRegister(NZCV);
885 nzcv().C());
981 nzcv().SetRawValue(FPUnorderedFlag);
983 nzcv().SetRawValue(FPLessThanFlag)
[all...] |
| disasm-arm64.cc | 1162 case NZCV: form = "'Xt, nzcv"; break;
1171 case NZCV: form = "nzcv, 'Xt"; break;
1440 int nzcv = (instr->Nzcv() << Flags_offset); local
[all...] |
| simulator-arm64.h | 82 // The proper way to initialize a simulated system register (such as NZCV) is as
84 // SimSystemRegister nzcv = SimSystemRegister::DefaultValueFor(NZCV);
491 SimSystemRegister& nzcv() { return nzcv_; }
609 SimSystemRegister& flags = nzcv();
|
| macro-assembler-arm64-inl.h | 127 StatusFlags nzcv,
131 ConditionalCompareMacro(rn, -operand.ImmediateValue(), nzcv, cond, CCMN);
133 ConditionalCompareMacro(rn, operand, nzcv, cond, CCMP);
140 StatusFlags nzcv,
144 ConditionalCompareMacro(rn, -operand.ImmediateValue(), nzcv, cond, CCMP);
146 ConditionalCompareMacro(rn, operand, nzcv, cond, CCMN);
558 StatusFlags nzcv,
562 fccmp(fn, fm, nzcv, cond);
[all...] |
| /external/vixl/src/vixl/a64/ |
| simulator-a64.cc | 51 case NZCV:
104 nzcv_ = SimSystemRegister::DefaultValueFor(NZCV);
322 nzcv().SetN(N);
323 nzcv().SetZ(Z);
324 nzcv().SetC(C);
325 nzcv().SetV(V);
326 LogSystemRegister(NZCV);
408 nzcv().SetRawValue(FPUnorderedFlag);
414 nzcv().SetRawValue(FPLessThanFlag);
416 nzcv().SetRawValue(FPGreaterThanFlag)
[all...] |
| /external/valgrind/VEX/priv/ |
| guest_arm_defs.h | 82 /* Calculate NZCV from the supplied thunk components, in the positions
133 details of the most recent flag-setting operation, so NZCV can
174 ARMG_CC_OP_COPY=0, /* DEP1 = NZCV in 31:28, DEP2 = 0, DEP3 = 0
|
| guest_arm64_defs.h | 80 /* Calculate NZCV from the supplied thunk components, in the positions
123 /* Flag masks. Defines positions of flag bits in the NZCV
138 details of the most recent flag-setting operation, so NZCV can
179 ARM64G_CC_OP_COPY=0, /* DEP1 = NZCV in 31:28, DEP2 = 0, DEP3 = 0
|
| guest_arm64_helpers.c | 120 /* (nzcv:28x0, unused, unused) */
238 /* (nzcv:28x0, unused, unused) */
357 /* (nzcv:28x0, unused, unused) */
467 /* (nzcv:28x0, unused, unused) */
573 /* Calculate NZCV from the supplied thunk components, in the positions
1160 ULong nzcv = 0; local
[all...] |
| /bionic/libc/arch-arm64/generic/bionic/ |
| strncmp.S | 212 ccmp data1w, #1, #0, cs /* NZCV = 0b0000. */
213 ccmp data1w, data2w, #0, cs /* NZCV = 0b0000. */
|
| /external/llvm/lib/CodeGen/ |
| MachineCSE.cpp | 603 // subs ... %NZCV<imp-def> <- CSMI
604 // csinc ... %NZCV<imp-use,kill> <- this kill flag isn't valid anymore
605 // subs ... %NZCV<imp-def> <- MI, to be eliminated
606 // csinc ... %NZCV<imp-use,kill>
608 // (here %NZCV), that register, if it was killed before MI, should have
|
| /external/vixl/test/ |
| test-assembler-a64.cc | [all...] |
| /art/runtime/arch/arm64/ |
| memcmp16_arm64.S | 137 ccmp data1w, data2w, #0, cs /* NZCV = 0b0000. */
|
