| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vecFold.ll | 80 define <8 x i16> @raddhn(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %b0, <4 x i32> %b1) nounwind readnone ssp {
81 ; CHECK-LABEL: raddhn:
83 ; CHECK: raddhn.4h v0, v0, v1
86 %vraddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a0, <4 x i32> %a1) nounwind
87 %vraddhn2.i10 = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %b0, <4 x i32> %b1) nounwind
142 declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
|
| arm64-vadd.ll | 67 ;CHECK: raddhn.8b
70 %tmp3 = call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
76 ;CHECK: raddhn.4h
79 %tmp3 = call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
85 ;CHECK: raddhn.2s
88 %tmp3 = call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
94 ;CHECK: raddhn.8b
96 %vraddhn2.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
97 %vraddhn_high2.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
104 ;CHECK: raddhn.4
[all...] |
| arm64-neon-3vdiff.ll | 47 declare <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64>, <2 x i64>)
49 declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>)
51 declare <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16>, <8 x i16>)
691 ; CHECK: raddhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
693 %vraddhn2.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b)
699 ; CHECK: raddhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
701 %vraddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b)
707 ; CHECK: raddhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
709 %vraddhn2.i = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b)
715 ; CHECK: raddhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8
[all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-3vdiff.s | 385 raddhn v0.8b, v1.8h, v2.8h
386 raddhn v0.4h, v1.4s, v2.4s
387 raddhn v0.2s, v1.2d, v2.2d
389 // CHECK: raddhn v0.8b, v1.8h, v2.8h // encoding: [0x20,0x40,0x22,0x2e]
390 // CHECK: raddhn v0.4h, v1.4s, v2.4s // encoding: [0x20,0x40,0x62,0x2e]
391 // CHECK: raddhn v0.2s, v1.2d, v2.2d // encoding: [0x20,0x40,0xa2,0x2e]
|
| neon-diagnostics.s | [all...] |
| /external/libmpeg2/common/armv8/ |
| impeg2_idct.s | 242 raddhn v12.4h, v0.4s, v8.4s
252 raddhn v12.4h, v0.4s, v8.4s
262 raddhn v12.4h, v0.4s, v8.4s
272 raddhn v12.4h, v0.4s, v8.4s
282 raddhn v12.4h, v0.4s, v8.4s
292 raddhn v12.4h, v0.4s, v8.4s
302 raddhn v12.4h, v0.4s, v8.4s
312 raddhn v12.4h, v0.4s, v8.4s
[all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/vixl/src/vixl/a64/ |
| macro-assembler-a64.h | [all...] |
| disasm-a64.cc | [all...] |
| simulator-a64.h | [all...] |
| assembler-a64.h | [all...] |
| logic-a64.cc | 3325 LogicVRegister Simulator::raddhn(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| simulator-a64.cc | [all...] |
| assembler-a64.cc | [all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | 613 #include "traces/a64/sim-raddhn-2s-trace-a64.h"
614 #include "traces/a64/sim-raddhn-4h-trace-a64.h"
615 #include "traces/a64/sim-raddhn-8b-trace-a64.h"
[all...] |
| test-disasm-a64.cc | [all...] |
| test-simulator-a64.cc | [all...] |
| /external/clang/test/CodeGen/ |
| aarch64-neon-intrinsics.c | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| fp_and_simd.stdout.exp | [all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| neon-instructions.txt | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.td | [all...] |
| /prebuilts/android-emulator/linux-x86_64/lib/gles_mesa/ |
| libGL.so | |
| libGL.so.1 | |
| libosmesa.so | |
