| /external/strace/linux/powerpc/ |
| userent.h | 4 #define REGSIZE (sizeof(unsigned long))
5 { REGSIZE*PT_R0, "r0" },
6 { REGSIZE*PT_R1, "r1" },
7 { REGSIZE*PT_R2, "r2" },
8 { REGSIZE*PT_R3, "r3" },
9 { REGSIZE*PT_R4, "r4" },
10 { REGSIZE*PT_R5, "r5" },
11 { REGSIZE*PT_R6, "r6" },
12 { REGSIZE*PT_R7, "r7" },
13 { REGSIZE*PT_R8, "r8" }
[all...] |
| /development/scripts/gdb/ |
| dalvik.gdb | 27 set $regSize = ((Method *) $method)->registersSize
30 while $index < $regSize
32 if $regSize - $index <= $insSize
33 printf " (in%d)\n", $insSize - $regSize + $index
|
| /dalvik/dexgen/src/com/android/dexgen/dex/file/ |
| DebugInfoDecoder.java | 72 private final int regSize;
88 * @param regSize register size, in register units, of the register space
94 DebugInfoDecoder(byte[] encoded, int codesize, int regSize,
104 this.regSize = regSize;
109 lastEntryForReg = new LocalEntry[regSize];
230 * {@code regSize}
235 return regSize
|
| DebugInfoEncoder.java | 67 private final int regSize;
104 * @param regSize
109 DexFile file, int codeSize, int regSize,
117 this.regSize = regSize;
120 lastEntryForReg = new LocalList.Entry[regSize];
510 * {@code regSize}
515 return regSize
531 BitSet seen = new BitSet(regSize - argBase);
|
| DebugInfoItem.java | 179 int regSize = insns.getRegistersSize();
183 file, codeSize, regSize, isStatic, ref);
|
| /dalvik/dx/src/com/android/dx/dex/file/ |
| DebugInfoDecoder.java | 83 private final int regSize;
99 * @param regSize register size, in register units, of the register space
105 DebugInfoDecoder(byte[] encoded, int codesize, int regSize,
115 this.regSize = regSize;
120 lastEntryForReg = new LocalEntry[regSize];
240 * {@code regSize}
245 return regSize
|
| DebugInfoEncoder.java | 75 private final int regSize;
112 * @param regSize
117 DexFile file, int codeSize, int regSize,
125 this.regSize = regSize;
128 lastEntryForReg = new LocalList.Entry[regSize];
518 * {@code regSize}
523 return regSize
539 BitSet seen = new BitSet(regSize - argBase);
|
| DebugInfoItem.java | 176 int regSize = insns.getRegistersSize();
180 file, codeSize, regSize, isStatic, ref);
|
| /external/dexmaker/src/dx/java/com/android/dx/dex/file/ |
| DebugInfoDecoder.java | 73 private final int regSize;
89 * @param regSize register size, in register units, of the register space
95 DebugInfoDecoder(byte[] encoded, int codesize, int regSize,
105 this.regSize = regSize;
110 lastEntryForReg = new LocalEntry[regSize];
230 * {@code regSize}
235 return regSize
|
| DebugInfoEncoder.java | 67 private final int regSize;
104 * @param regSize
109 DexFile file, int codeSize, int regSize,
117 this.regSize = regSize;
120 lastEntryForReg = new LocalList.Entry[regSize];
510 * {@code regSize}
515 return regSize
531 BitSet seen = new BitSet(regSize - argBase);
|
| DebugInfoItem.java | 177 int regSize = insns.getRegistersSize();
181 file, codeSize, regSize, isStatic, ref);
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize,
216 (RegSize != 64 && (Imm >> RegSize != 0 || Imm == ~0U)))
220 unsigned Size = RegSize;
274 static inline bool isLogicalImmediate(uint64_t imm, unsigned regSize) {
276 return processLogicalImmediate(imm, regSize, encoding);
281 static inline uint64_t encodeLogicalImmediate(uint64_t imm, unsigned regSize) {
283 bool res = processLogicalImmediate(imm, regSize, encoding);
291 /// integer value it represents with regSize bits.
292 static inline uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize) {
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 61 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
63 unsigned MFLoOpc, unsigned RegSize);
180 unsigned RegSize) {
188 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
199 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
205 unsigned RegSize) {
213 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
223 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfExpression.cpp | 131 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8;
134 SmallBitVector Coverage(RegSize, false);
143 SmallBitVector Intersection(RegSize, false);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 632 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
633 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
634 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
636 explicit operator bool() const { return RegSize; }
638 unsigned RegSize, ImmLSB, ImmSize;
722 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
724 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
726 if (And.RegSize == 64) {
[all...] |
| /external/valgrind/coregrind/ |
| vgdb-invoker-ptrace.c | 886 const int regsize = 4; local
889 sp = sp - regsize;
891 assert(regsize == sizeof(check));
894 regsize);
901 sp = sp - regsize;
907 regsize);
973 const int regsize = 8;
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 41 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
82 unsigned getSize() const { return RegSize; }
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | [all...] |
| AArch64RegisterInfo.td | 470 class TypedVecListAsmOperand<int count, int regsize, int lanes, string kind>
476 let RenderMethod = "addVectorList" # regsize # "Operands<" # count # ">";
|
| AArch64LoadStoreOptimizer.cpp | 821 unsigned RegSize = TII->getRegClass(MemMI->getDesc(), 0, TRI, MF)->getSize();
849 if (isMatchingUpdateInsn(MI, BaseReg, RegSize))
[all...] |
| /external/libunwind/src/ia64/ |
| Gparser.c | 165 alloc_spill_area (unsigned long *offp, unsigned long regsize,
175 *offp -= regsize;
|
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 140 int RegSize;
143 RegSize = 8;
147 RegSize = 4;
160 count += RegSize;
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_ra.cpp | 52 inline unsigned int getFileSize(DataFile f, uint8_t regSize) const
54 if (restrictedGPR16Range && f == FILE_GPR && regSize == 2)
[all...] |
| /external/v8/src/arm64/ |
| constants-arm64.h | 43 // TODO(all): k<Y>RegSize should probably be k<Y>RegSizeInBits.
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 717 unsigned RegSize = RegisterVT.getSizeInBits();
721 if (NumZeroBits == RegSize) {
733 if (NumSignBits == RegSize)
735 else if (NumZeroBits >= RegSize-1)
737 else if (NumSignBits > RegSize-8)
739 else if (NumZeroBits >= RegSize-8)
741 else if (NumSignBits > RegSize-16)
743 else if (NumZeroBits >= RegSize-16)
745 else if (NumSignBits > RegSize-32)
747 else if (NumZeroBits >= RegSize-32
[all...] |
