/external/llvm/test/CodeGen/AArch64/ |
arm64-vaddlv.ll | 5 ; CHECK: saddlp.1d v[[REGNUM:[0-9]+]], v[[INREG:[0-9]+]]
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arm64-vadd.ll | 429 ;CHECK: saddlp.4h 431 %tmp3 = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> %tmp1) 437 ;CHECK: saddlp.2s 439 %tmp3 = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> %tmp1) 445 ;CHECK: saddlp.1d 447 %tmp3 = call <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32> %tmp1) 453 ;CHECK: saddlp.8h 455 %tmp3 = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> %tmp1) 461 ;CHECK: saddlp.4s 463 %tmp3 = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> %tmp1 [all...] |
/external/llvm/test/MC/AArch64/ |
neon-simd-misc.s | 43 saddlp v3.8h, v21.16b 44 saddlp v8.4h, v5.8b 45 saddlp v9.4s, v1.8h 46 saddlp v0.2s, v1.4h 47 saddlp v12.2d, v4.4s 48 saddlp v17.1d, v28.2s 50 // CHECK: saddlp v3.8h, v21.16b // encoding: [0xa3,0x2a,0x20,0x4e] 51 // CHECK: saddlp v8.4h, v5.8b // encoding: [0xa8,0x28,0x20,0x0e] 52 // CHECK: saddlp v9.4s, v1.8h // encoding: [0x29,0x28,0x60,0x4e] 53 // CHECK: saddlp v0.2s, v1.4h // encoding: [0x20,0x28,0x60,0x0e [all...] |
arm64-advsimd.s | 493 saddlp.4h v0, v0 543 ; CHECK: saddlp.4h v0, v0 ; encoding: [0x00,0x28,0x20,0x0e] [all...] |
/external/libavc/common/armv8/ |
ih264_intra_pred_luma_16x16_av8.s | 450 saddlp v0.2s, v0.4h 454 saddlp v0.1d, v0.2s
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/external/clang/test/CodeGen/ |
aarch64-neon-misc.c | 672 // CHECK: saddlp v{{[0-9]+}}.4h, v{{[0-9]+}}.8b 678 // CHECK: saddlp v{{[0-9]+}}.2s, v{{[0-9]+}}.4h 684 // CHECK: saddlp v{{[0-9]+}}.1d, v{{[0-9]+}}.2s 708 // CHECK: saddlp v{{[0-9]+}}.8h, v{{[0-9]+}}.16b 714 // CHECK: saddlp v{{[0-9]+}}.4s, v{{[0-9]+}}.8h 720 // CHECK: saddlp v{{[0-9]+}}.2d, v{{[0-9]+}}.4s [all...] |
/external/llvm/include/llvm/IR/ |
IntrinsicsAArch64.td | 282 // FIXME: In theory, we shouldn't need intrinsics for saddlp or
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/external/vixl/test/ |
test-simulator-traces-a64.h | 678 #include "traces/a64/sim-saddlp-1d-trace-a64.h" 679 #include "traces/a64/sim-saddlp-2d-trace-a64.h" 680 #include "traces/a64/sim-saddlp-2s-trace-a64.h" 681 #include "traces/a64/sim-saddlp-4h-trace-a64.h" 682 #include "traces/a64/sim-saddlp-4s-trace-a64.h" 683 #include "traces/a64/sim-saddlp-8h-trace-a64.h" [all...] |
test-simulator-a64.cc | [all...] |
test-disasm-a64.cc | [all...] |
/external/valgrind/none/tests/arm64/ |
fp_and_simd.c | [all...] |
fp_and_simd.stdout.exp | [all...] |
/external/vixl/doc/ |
supported-instructions.md | [all...] |
/external/vixl/src/vixl/a64/ |
macro-assembler-a64.h | [all...] |
disasm-a64.cc | [all...] |
simulator-a64.h | [all...] |
assembler-a64.h | [all...] |
logic-a64.cc | 2300 LogicVRegister Simulator::saddlp(VectorFormat vform, function in class:vixl::Simulator [all...] |
simulator-a64.cc | [all...] |
assembler-a64.cc | [all...] |
/prebuilts/gcc/darwin-x86/aarch64/aarch64-linux-android-4.9/lib/gcc/aarch64-linux-android/4.9.x-google/include/ |
arm_neon.h | [all...] |
/prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9/lib/gcc/aarch64-linux-android/4.9.x-google/include/ |
arm_neon.h | [all...] |
/external/llvm/test/MC/Disassembler/AArch64/ |
arm64-advsimd.txt | 491 # CHECK: saddlp.4h v0, v0 [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.td | [all...] |
/prebuilts/android-emulator/linux-x86_64/lib/gles_mesa/ |
libGL.so | |