| /external/llvm/test/MC/AArch64/ |
| neon-scalar-by-elem-saturating-mul.s | 27 sqdmulh h0, h1, v0.h[0]
28 sqdmulh h10, h11, v10.h[4]
29 sqdmulh h20, h21, v15.h[7]
30 sqdmulh s25, s26, v27.s[3]
31 sqdmulh s2, s6, v7.s[0]
33 // CHECK: sqdmulh h0, h1, v0.h[0] // encoding: [0x20,0xc0,0x40,0x5f]
34 // CHECK: sqdmulh h10, h11, v10.h[4] // encoding: [0x6a,0xc9,0x4a,0x5f]
35 // CHECK: sqdmulh h20, h21, v15.h[7] // encoding: [0xb4,0xca,0x7f,0x5f]
36 // CHECK: sqdmulh s25, s26, v27.s[3] // encoding: [0x59,0xcb,0xbb,0x5f]
37 // CHECK: sqdmulh s2, s6, v7.s[0] // encoding: [0xc2,0xc0,0x87,0x5f
[all...] |
| neon-scalar-mul.s | 9 sqdmulh h10, h11, h12
10 sqdmulh s20, s21, s2
12 // CHECK: sqdmulh h10, h11, h12 // encoding: [0x6a,0xb5,0x6c,0x5e]
13 // CHECK: sqdmulh s20, s21, s2 // encoding: [0xb4,0xb6,0xa2,0x5e]
|
| neon-mul-div-instructions.s | 57 sqdmulh v2.4h, v25.4h, v3.4h
58 sqdmulh v12.8h, v5.8h, v13.8h
59 sqdmulh v3.2s, v1.2s, v30.2s
61 // CHECK: sqdmulh v2.4h, v25.4h, v3.4h // encoding: [0x22,0xb7,0x63,0x0e]
62 // CHECK: sqdmulh v12.8h, v5.8h, v13.8h // encoding: [0xac,0xb4,0x6d,0x4e]
63 // CHECK: sqdmulh v3.2s, v1.2s, v30.2s // encoding: [0x23,0xb4,0xbe,0x0e]
|
| neon-2velem.s | 245 sqdmulh v0.4h, v1.4h, v2.h[2]
246 sqdmulh v0.8h, v1.8h, v2.h[2]
247 sqdmulh v0.2s, v1.2s, v2.s[2]
248 sqdmulh v0.2s, v1.2s, v22.s[2]
249 sqdmulh v0.4s, v1.4s, v2.s[2]
250 sqdmulh v0.4s, v1.4s, v22.s[2]
252 // CHECK: sqdmulh v0.4h, v1.4h, v2.h[2] // encoding: [0x20,0xc0,0x62,0x0f]
253 // CHECK: sqdmulh v0.8h, v1.8h, v2.h[2] // encoding: [0x20,0xc0,0x62,0x4f]
254 // CHECK: sqdmulh v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0xc8,0x82,0x0f]
255 // CHECK: sqdmulh v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0xc8,0x96,0x0f
[all...] |
| arm64-advsimd.s | 347 sqdmulh.4h v0, v0, v0
418 ; CHECK: sqdmulh.4h v0, v0, v0 ; encoding: [0x00,0xb4,0x60,0x0e]
[all...] |
| neon-diagnostics.s | [all...] |
| /external/clang/test/CodeGen/ |
| aarch64-neon-scalar-x-indexed-elem.c | 159 // CHECK: sqdmulh {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[3]
165 // CHECK: sqdmulh {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
172 // CHECK: sqdmulh {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[7]
179 // CHECK: sqdmulh {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
|
| aarch64-neon-2velem.c | 683 // CHECK: sqdmulh {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
689 // CHECK: sqdmulh {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]
695 // CHECK: sqdmulh {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
701 // CHECK: sqdmulh {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-neon-mul-div.ll | 704 declare <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16>, <4 x i16>)
705 declare <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16>, <8 x i16>)
706 declare <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32>, <2 x i32>)
707 declare <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32>, <4 x i32>)
711 %prod = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
712 ; CHECK: sqdmulh v0.4h, v0.4h, v1.4h
718 %prod = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
719 ; CHECK: sqdmulh v0.8h, v0.8h, v1.8h
725 %prod = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
726 ; CHECK: sqdmulh v0.2s, v0.2s, v1.2
[all...] |
| arm64-vmul.ll | 123 ;CHECK: sqdmulh.4h
126 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
132 ;CHECK: sqdmulh.8h
135 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
141 ;CHECK: sqdmulh.2s
144 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
150 ;CHECK: sqdmulh.4s
153 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
159 ;CHECK: sqdmulh s0, {{s[0-9]+}}, {{s[0-9]+}}
162 %tmp3 = call i32 @llvm.aarch64.neon.sqdmulh.i32(i32 %tmp1, i32 %tmp2
[all...] |
| arm64-neon-2velem.ll | 17 declare <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32>, <4 x i32>)
19 declare <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32>, <2 x i32>)
21 declare <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16>, <8 x i16>)
23 declare <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16>, <4 x i16>)
[all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | [all...] |
| test-disasm-a64.cc | [all...] |
| test-simulator-a64.cc | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | 330 # CHECK: sqdmulh.4h v0, v0, v0
[all...] |
| neon-instructions.txt | 657 # CHECK: sqdmulh v31.2s, v31.2s, v31.2s
658 # CHECK: sqdmulh v5.4s, v7.4s, v9.4s
[all...] |
| /external/vixl/src/vixl/a64/ |
| disasm-a64.cc | [all...] |
| macro-assembler-a64.h | [all...] |
| simulator-a64.cc | [all...] |
| logic-a64.cc | 1079 LogicVRegister Simulator::sqdmulh(VectorFormat vform, function in class:vixl::Simulator
3295 LogicVRegister Simulator::sqdmulh(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| simulator-a64.h | [all...] |
| assembler-a64.h | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/valgrind/VEX/priv/ |
| host_arm64_defs.c | 659 case ARM64vecb_SQDMULH32x4: *nm = "sqdmulh"; *ar = "4s"; return;
660 case ARM64vecb_SQDMULH16x8: *nm = "sqdmulh"; *ar = "8h"; return;
[all...] |
