| /external/llvm/test/MC/AArch64/ |
| neon-scalar-by-elem-saturating-mul.s | 6 sqdmull s1, h1, v1.h[1]
7 sqdmull s8, h2, v5.h[2]
8 sqdmull s12, h17, v9.h[3]
9 sqdmull s31, h31, v15.h[7]
10 sqdmull d1, s1, v4.s[0]
11 sqdmull d31, s31, v31.s[3]
12 sqdmull d9, s10, v15.s[0]
15 // CHECK: sqdmull s1, h1, v1.h[1] // encoding: [0x21,0xb0,0x51,0x5f]
16 // CHECK: sqdmull s8, h2, v5.h[2] // encoding: [0x48,0xb0,0x65,0x5f]
17 // CHECK: sqdmull s12, h17, v9.h[3] // encoding: [0x2c,0xb2,0x79,0x5f
[all...] |
| neon-scalar-mul.s | 59 sqdmull s12, h22, h12
60 sqdmull d15, s22, s12
62 // CHECK: sqdmull s12, h22, h12 // encoding: [0xcc,0xd2,0x6c,0x5e]
63 // CHECK: sqdmull d15, s22, s12 // encoding: [0xcf,0xd2,0xac,0x5e]
|
| neon-2velem.s | 231 sqdmull v0.4s, v1.4h, v2.h[2]
232 sqdmull v0.2d, v1.2s, v2.s[2]
233 sqdmull v0.2d, v1.2s, v22.s[2]
238 // CHECK: sqdmull v0.4s, v1.4h, v2.h[2] // encoding: [0x20,0xb0,0x62,0x0f]
239 // CHECK: sqdmull v0.2d, v1.2s, v2.s[2] // encoding: [0x20,0xb8,0x82,0x0f]
240 // CHECK: sqdmull v0.2d, v1.2s, v22.s[2] // encoding: [0x20,0xb8,0x96,0x0f]
|
| arm64-advsimd.s | [all...] |
| neon-3vdiff.s | 269 sqdmull v0.4s, v1.4h, v2.4h
270 sqdmull v0.2d, v1.2s, v2.2s
272 // CHECK: sqdmull v0.4s, v1.4h, v2.4h // encoding: [0x20,0xd0,0x62,0x0e]
273 // CHECK: sqdmull v0.2d, v1.2s, v2.2s // encoding: [0x20,0xd0,0xa2,0x0e]
|
| neon-diagnostics.s | [all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| machine-copy-prop.ll | 32 %sqdmull = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> <i16 1, i16 0, i16 0, i16 0>, <4 x i16> <i16 2, i16 0, i16 0, i16 0>)
33 %sqadd = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> zeroinitializer, <4 x i32> %sqdmull)
85 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
|
| arm64-neon-2velem-high.ll | 7 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>)
11 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
89 %vqdmull15.i.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)
101 %vqdmull9.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)
170 %vqdmlal15.i.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)
182 %vqdmlal9.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)
248 %vqdmlsl15.i.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)
260 %vqdmlsl9.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)
|
| arm64-vmul.ll | 68 ;CHECK: sqdmull.4s
71 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
77 ;CHECK: sqdmull.2d
80 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
91 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
102 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
107 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
108 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
309 %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
320 %tmp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2
[all...] |
| arm64-neon-2velem.ll | 25 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>)
27 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
[all...] |
| arm64-neon-3vdiff.ll | 5 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>)
9 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
[all...] |
| /external/clang/test/CodeGen/ |
| aarch64-neon-scalar-x-indexed-elem.c | 135 // CHECK: sqdmull {{s[0-9]+|v[0-9]+.4s}}, {{h[0-9]+|v[0-9].4h}}, {{v[0-9]+}}.h[3]
141 // CHECK: sqdmull {{d[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
147 // CHECK: sqdmull {{s[0-9]+|v[0-9]+.4s}}, {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[7]
153 // CHECK: sqdmull {{d[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
|
| arm64-scalar-test.c | 168 // CHECK: sqdmull.4s {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
174 // CHECK: sqdmull {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
| aarch64-neon-2velem.c | 635 // CHECK: sqdmull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
641 // CHECK: sqdmull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
647 // CHECK: sqdmull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
653 // CHECK: sqdmull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
[all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | [all...] |
| neon-instructions.txt | [all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | [all...] |
| test-disasm-a64.cc | [all...] |
| test-simulator-a64.cc | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/vixl/src/vixl/a64/ |
| disasm-a64.cc | [all...] |
| macro-assembler-a64.h | [all...] |
| logic-a64.cc | 1007 LogicVRegister Simulator::sqdmull(VectorFormat vform, function in class:vixl::Simulator
3245 LogicVRegister Simulator::sqdmull(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| simulator-a64.cc | [all...] |
