| /external/llvm/test/CodeGen/AArch64/ |
| arm64-sqshl-uqshl-i64Contant.ll | 3 ; Check if sqshl/uqshl with constant shift amout can be selected.
6 ; CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
7 %1 = tail call i64 @llvm.aarch64.neon.sqshl.i64(i64 %a, i64 36)
19 declare i64 @llvm.aarch64.neon.sqshl.i64(i64, i64)
|
| arm64-vshift.ll | 5 ;CHECK: sqshl.8b
8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
14 ;CHECK: sqshl.4h
17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
23 ;CHECK: sqshl.2s
26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
59 ;CHECK: sqshl.16b
62 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
68 ;CHECK: sqshl.8h
71 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2
[all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-saturating-shift.s | 9 sqshl v0.8b, v1.8b, v2.8b
10 sqshl v0.16b, v1.16b, v2.16b
11 sqshl v0.4h, v1.4h, v2.4h
12 sqshl v0.8h, v1.8h, v2.8h
13 sqshl v0.2s, v1.2s, v2.2s
14 sqshl v0.4s, v1.4s, v2.4s
15 sqshl v0.2d, v1.2d, v2.2d
17 // CHECK: sqshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x4c,0x22,0x0e]
18 // CHECK: sqshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x4c,0x22,0x4e]
19 // CHECK: sqshl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x4c,0x62,0x0e
[all...] |
| neon-scalar-saturating-shift.s | 6 sqshl b0, b1, b2
7 sqshl h10, h11, h12
8 sqshl s20, s21, s2
9 sqshl d17, d31, d8
11 // CHECK: sqshl b0, b1, b2 // encoding: [0x20,0x4c,0x22,0x5e]
12 // CHECK: sqshl h10, h11, h12 // encoding: [0x6a,0x4d,0x6c,0x5e]
13 // CHECK: sqshl s20, s21, s2 // encoding: [0xb4,0x4e,0xa2,0x5e]
14 // CHECK: sqshl d17, d31, d8 // encoding: [0xf1,0x4f,0xe8,0x5e]
|
| neon-scalar-shift-imm.s | 71 sqshl b11, b19, #7
72 sqshl h13, h18, #11
73 sqshl s14, s17, #22
74 sqshl d15, d16, #51
76 // CHECK: sqshl b11, b19, #7 // encoding: [0x6b,0x76,0x0f,0x5f]
77 // CHECK: sqshl h13, h18, #11 // encoding: [0x4d,0x76,0x1b,0x5f]
78 // CHECK: sqshl s14, s17, #22 // encoding: [0x2e,0x76,0x36,0x5f]
79 // CHECK: sqshl d15, d16, #51 // encoding: [0x0f,0x76,0x73,0x5f]
|
| neon-simd-shift.s | 221 sqshl v0.8b, v1.8b, #3
222 sqshl v0.4h, v1.4h, #3
223 sqshl v0.2s, v1.2s, #3
224 sqshl v0.16b, v1.16b, #3
225 sqshl v0.8h, v1.8h, #3
226 sqshl v0.4s, v1.4s, #3
227 sqshl v0.2d, v1.2d, #3
229 // CHECK: sqshl v0.8b, v1.8b, #3 // encoding: [0x20,0x74,0x0b,0x0f]
230 // CHECK: sqshl v0.4h, v1.4h, #3 // encoding: [0x20,0x74,0x13,0x0f]
231 // CHECK: sqshl v0.2s, v1.2s, #3 // encoding: [0x20,0x74,0x23,0x0f
[all...] |
| arm64-advsimd.s | 350 sqshl.8b v0, v0, v0
421 ; CHECK: sqshl.8b v0, v0, v0 ; encoding: [0x00,0x4c,0x20,0x0e]
[all...] |
| neon-diagnostics.s | [all...] |
| /external/clang/test/CodeGen/ |
| arm64_vshift.c | 6 // CHECK: call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> %in, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
12 // CHECK: call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> %in, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
18 // CHECK: call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> %in, <2 x i32> <i32 1, i32 1>)
24 // CHECK: call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> %in, <1 x i64> <i64 1>)
31 // CHECK: call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> %in, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
37 // CHECK: call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> %in, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
43 // CHECK: call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> %in, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
49 // CHECK: call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> %in, <2 x i64> <i64 1, i64 1>
|
| arm64-scalar-test.c | 96 // CHECK: sqshl.8b {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
102 // CHECK: sqshl.4h {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
108 // CHECK: sqshl {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
114 // CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
120 // CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
|
| aarch64-neon-intrinsics.c | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | [all...] |
| test-disasm-a64.cc | [all...] |
| test-simulator-a64.cc | [all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | 333 # CHECK: sqshl.8b v0, v0, v0
[all...] |
| neon-instructions.txt | 400 # CHECK: sqshl v1.8b, v15.8b, v22.8b
402 # CHECK: sqshl v3.4h, v13.4h, v24.4h
404 # CHECK: sqshl v5.2s, v11.2s, v26.2s
462 # CHECK: sqshl d31, d31, d31
464 # CHECK: sqshl h3, h4, h15
918 # CHECK: sqshl v0.8b, v1.8b, #3
919 # CHECK: sqshl v0.4h, v1.4h, #3
920 # CHECK: sqshl v0.2s, v1.2s, #3
921 # CHECK: sqshl v0.16b, v1.16b, #3
922 # CHECK: sqshl v0.8h, v1.8h, #
[all...] |
| /external/vixl/src/vixl/a64/ |
| disasm-a64.cc | [all...] |
| macro-assembler-a64.h | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/valgrind/VEX/priv/ |
| host_arm64_defs.c | 663 case ARM64vecb_SQSHL64x2: *nm = "sqshl "; *ar = "2d"; return;
664 case ARM64vecb_SQSHL32x4: *nm = "sqshl "; *ar = "4s"; return;
665 case ARM64vecb_SQSHL16x8: *nm = "sqshl "; *ar = "8h"; return;
666 case ARM64vecb_SQSHL8x16: *nm = "sqshl "; *ar = "16b"; return;
[all...] |
| guest_arm64_toIR.c | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64SchedCyclone.td | 488 // SQSHL,SQSHLU,UQSHL are WriteV.
|
| AArch64InstrInfo.td | [all...] |
| /frameworks/rs/driver/runtime/arch/ |
| asimd.ll | 26 declare <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
27 declare <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
28 declare <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
[all...] |
