| /external/libhevc/decoder/arm64/ |
| ihevcd_fmt_conv_420sp_to_rgba8888.s | 213 sqshrn2 v5.8h, v7.4s,#13 ////D9 = (U-128)*C4>>13 4 16-BIT VALUES
218 sqshrn2 v7.8h, v22.4s,#13 ////D11 = (V-128)*C1>>13 4 16-BIT VALUES
223 sqshrn2 v12.8h, v14.4s,#13 ////D13 = [(U-128)*C2 + (V-128)*C3]>>13 4 16-BIT VALUES
376 sqshrn2 v5.8h, v7.4s,#13 ////D9 = (U-128)*C4>>13 4 16-BIT VALUES
381 sqshrn2 v7.8h, v22.4s,#13 ////D11 = (V-128)*C1>>13 4 16-BIT VALUES
386 sqshrn2 v12.8h, v14.4s,#13 ////D13 = [(U-128)*C2 + (V-128)*C3]>>13 4 16-BIT VALUES
|
| /external/clang/test/CodeGen/ |
| arm64_neon_high_half.c | 337 // CHECK: sqshrn2.16b
342 // CHECK: sqshrn2.8h
347 // CHECK: sqshrn2.4s
|
| aarch64-neon-intrinsics.c | [all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-simd-shift.s | 335 sqshrn2 v0.16b, v1.8h, #3
336 sqshrn2 v0.8h, v1.4s, #3
337 sqshrn2 v0.4s, v1.2d, #3
342 // CHECK: sqshrn2 v0.16b, v1.8h, #3 // encoding: [0x20,0x94,0x0d,0x4f]
343 // CHECK: sqshrn2 v0.8h, v1.4s, #3 // encoding: [0x20,0x94,0x1d,0x4f]
344 // CHECK: sqshrn2 v0.4s, v1.2d, #3 // encoding: [0x20,0x94,0x3d,0x4f]
|
| arm64-advsimd.s | [all...] |
| neon-diagnostics.s | [all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-neon-simd-shift.ll | 434 ; CHECK: sqshrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3
445 ; CHECK: sqshrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9
456 ; CHECK: sqshrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
|
| arm64-vshift.ll | 775 ;CHECK: sqshrn2.16b v0, {{v[0-9]+}}, #1
785 ;CHECK: sqshrn2.8h v0, {{v[0-9]+}}, #1
795 ;CHECK: sqshrn2.4s v0, {{v[0-9]+}}, #1
[all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_Resize.S | 74 sqshrn2 \dsthi, v13.4s, #8 + (16 - VERTBITS)
93 sqshrn2 \dst, v12.4s, #8 + (16 - VERTBITS)
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | [all...] |
| neon-instructions.txt | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/vixl/src/vixl/a64/ |
| macro-assembler-a64.h | [all...] |
| disasm-a64.cc | [all...] |
| simulator-a64.h | [all...] |
| assembler-a64.h | [all...] |
| logic-a64.cc | 2697 LogicVRegister Simulator::sqshrn2(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| simulator-a64.cc | [all...] |
| assembler-a64.cc | [all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | [all...] |
| test-disasm-a64.cc | [all...] |
| /prebuilts/gcc/darwin-x86/aarch64/aarch64-linux-android-4.9/lib/gcc/aarch64-linux-android/4.9.x-google/include/ |
| arm_neon.h | [all...] |
| /prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9/lib/gcc/aarch64-linux-android/4.9.x-google/include/ |
| arm_neon.h | [all...] |
| /prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9/x86_64-linux-gnu/aarch64-linux-android/lib/ |
| libopcodes.a | [all...] |
