| /external/llvm/test/CodeGen/AArch64/ |
| arm64-subvector-extend.ll | 19 ; CHECK-NEXT: sshll.8h v0, v0, #0
37 ; CHECK-NEXT: sshll.8h v0, v0, #0
57 ; CHECK-NEXT: sshll.4s v0, v0, #0
75 ; CHECK-NEXT: sshll.4s v0, v0, #0
93 ; CHECK-NEXT: sshll.8h v0, v0, #0
95 ; CHECK-NEXT: sshll.4s v0, v0, #0
117 ; CHECK-NEXT: sshll.2d v0, v0, #0
135 ; CHECK-NEXT: sshll.4s v0, v0, #0
137 ; CHECK-NEXT: sshll.2d v0, v0, #0
|
| arm64-extend-int-to-fp.ll | 14 ; CHECK: sshll.4s v0, v0, #0
|
| arm64-vselect.ll | 11 ; sshll.4s v0, v0, #0
|
| complex-int-to-fp.ll | 15 ; CHECK: sshll.2d [[VAL64:v[0-9]+]], v0, #0
35 ; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
56 ; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
130 ; CHECK: sshll.4s [[VAL32:v[0-9]+]], v0, #0
150 ; CHECK: sshll.4s [[VAL32:v[0-9]+]], [[VAL16]], #0
|
| arm64-vbitwise.ll | 24 ;CHECK: sshll.8h
40 ;CHECK: sshll.4s
56 ;CHECK: sshll.2d
|
| arm64-scvt.ll | 409 ; CHECK-NEXT: sshll.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
410 ; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
428 ; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
470 ; CHECK-NEXT: sshll.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
471 ; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
489 ; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
544 ; CHECK-NEXT: sshll.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
545 ; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
563 ; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
604 ; CHECK-NEXT: sshll.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #
[all...] |
| neon-shift-left-long.ll | 5 ; CHECK: sshll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #3
13 ; CHECK: sshll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #9
21 ; CHECK: sshll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #19
107 ; CHECK: sshll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
114 ; CHECK: sshll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #0
121 ; CHECK: sshll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #0
|
| arm64-fast-isel-noconvert.ll | 15 ; CHECK: sshll.2d [[EXT:v[0-9]+]], v0, #0
|
| fp16-v8-instructions.ll | 259 ; CHECK-NEXT: sshll v[[REG1:[0-9]+]].8h, v0.8b, #0
261 ; CHECK-NEXT: sshll [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
275 ; CHECK-NEXT: sshll [[HI:v[0-9]+\.4s]], v0.4h, #0
|
| fp16-v4-instructions.ll | 138 ; CHECK-NEXT: sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0
149 ; CHECK-NEXT: sshll [[OP1:v[0-9]+\.4s]], v0.4h, #0
|
| arm64-vshift.ll | [all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-shift-left-long.s | 8 sshll v0.8h, v1.8b, #3
9 sshll v0.4s, v1.4h, #3
10 sshll v0.2d, v1.2s, #3
15 // CHECK: sshll v0.8h, v1.8b, #3 // encoding: [0x20,0xa4,0x0b,0x0f]
16 // CHECK: sshll v0.4s, v1.4h, #3 // encoding: [0x20,0xa4,0x13,0x0f]
17 // CHECK: sshll v0.2d, v1.2s, #3 // encoding: [0x20,0xa4,0x23,0x0f]
|
| neon-sxtl.s | 12 // CHECK: sshll v0.8h, v1.8b, #0 // encoding: [0x20,0xa4,0x08,0x0f]
13 // CHECK: sshll v0.4s, v1.4h, #0 // encoding: [0x20,0xa4,0x10,0x0f]
14 // CHECK: sshll v0.2d, v1.2s, #0 // encoding: [0x20,0xa4,0x20,0x0f]
|
| arm64-aliases.s | 678 ; CHECK: sshll.8h v1, v2, #0
680 ; CHECK: sshll.8h v1, v2, #0
683 ; CHECK: sshll.4s v1, v2, #0
685 ; CHECK: sshll.4s v1, v2, #0
688 ; CHECK: sshll.2d v1, v2, #0
690 ; CHECK: sshll.2d v1, v2, #0
|
| arm64-advsimd.s | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64SchedCyclone.td | 493 // SHLL,SSHLL,USHLL
|
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | [all...] |
| /external/vixl/test/ |
| test-disasm-a64.cc | [all...] |
| test-simulator-traces-a64.h | [all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_Resize.S | 420 sshll v11.4s, v9.4h, #2
|
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/vixl/src/vixl/a64/ |
| disasm-a64.cc | [all...] |
| macro-assembler-a64.h | [all...] |
| logic-a64.cc | 1612 LogicVRegister Simulator::sshll(VectorFormat vform, function in class:vixl::Simulator
[all...] |
