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  /external/llvm/lib/Target/Mips/
MipsRegisterInfo.cpp 53 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
54 return Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
85 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
86 if (Subtarget.isSingleFloat())
89 if (Subtarget.isABI_N64())
92 if (Subtarget.isABI_N32())
95 if (Subtarget.isFP64bit())
98 if (Subtarget.isFPXX())
107 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
108 if (Subtarget.isSingleFloat()
    [all...]
MipsTargetMachine.h 34 MipsSubtarget *Subtarget;
50 if (Subtarget)
51 return Subtarget;
57 /// \brief Reset the subtarget for the Mips target.
  /external/llvm/lib/Target/BPF/
BPFTargetMachine.h 23 BPFSubtarget Subtarget;
30 const BPFSubtarget *getSubtargetImpl() const { return &Subtarget; }
32 return &Subtarget;
CMakeLists.txt 10 tablegen(LLVM BPFGenSubtargetInfo.inc -gen-subtarget)
BPFSubtarget.cpp 1 //===-- BPFSubtarget.cpp - BPF Subtarget Information ----------------------===//
20 #define DEBUG_TYPE "bpf-subtarget"
  /external/llvm/lib/Target/SystemZ/
SystemZTargetMachine.h 27 SystemZSubtarget Subtarget;
36 const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; }
38 return &Subtarget;
  /external/llvm/lib/Target/XCore/
XCoreTargetMachine.h 24 XCoreSubtarget Subtarget;
32 const XCoreSubtarget *getSubtargetImpl() const { return &Subtarget; }
34 return &Subtarget;
CMakeLists.txt 9 tablegen(LLVM XCoreGenSubtargetInfo.inc -gen-subtarget)
XCoreSubtarget.cpp 1 //===-- XCoreSubtarget.cpp - XCore Subtarget Information ------------------===//
20 #define DEBUG_TYPE "xcore-subtarget"
  /external/llvm/lib/Target/MSP430/
CMakeLists.txt 8 tablegen(LLVM MSP430GenSubtargetInfo.inc -gen-subtarget)
MSP430Subtarget.cpp 1 //===-- MSP430Subtarget.cpp - MSP430 Subtarget Information ----------------===//
20 #define DEBUG_TYPE "msp430-subtarget"
MSP430TargetMachine.h 28 MSP430Subtarget Subtarget;
38 return &Subtarget;
  /external/llvm/lib/Target/PowerPC/
PPCRegisterInfo.cpp 103 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
105 if (Subtarget.hasVSX())
107 if (Subtarget.hasAltivec())
112 if (Subtarget.isDarwinABI())
114 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
116 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
123 ? (Subtarget.hasAltivec()
127 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList
134 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
136 if (Subtarget.hasVSX()
    [all...]
  /external/icu/icu4c/source/samples/
Makefile.in 72 subtarget=`echo $@ | sed s/-samples-recursive//`; \
74 echo "$(MAKE)[$(MAKELEVEL)]: Making \`$$subtarget' in \`$$subdir'"; \
77 local_target="$$subtarget-local"; \
79 local_target="$$subtarget"; \
84 $(MAKE) "$$subtarget-local" || exit; \
  /external/mesa3d/src/gallium/drivers/radeon/
AMDGPUTargetMachine.cpp 49 Subtarget(TT, CPU, FS),
50 DataLayout(Subtarget.getDataLayout()),
52 Subtarget.device()->getStackAlignment(), 0),
54 InstrItins(&Subtarget.getInstrItineraryData()),
59 if (Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
  /external/llvm/lib/Target/X86/
X86SelectionDAGInfo.cpp 60 const X86Subtarget &Subtarget =
78 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) {
83 V->isNullValue() ? Subtarget.getBZeroEntry() : nullptr) {
132 if (Subtarget.is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
161 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX,
164 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI,
209 // within a subtarget-specific limit.
211 const X86Subtarget &Subtarget =
216 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold())
247 AVT = Subtarget.is64Bit() ? MVT::i64 : MVT::i32
    [all...]
  /external/llvm/lib/Target/ARM/
ARMSelectionDAGInfo.cpp 35 const ARMSubtarget &Subtarget =
42 // within a subtarget-specific limit.
47 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold())
57 const unsigned MAX_LOADS_IN_LDM = Subtarget.isThumb1Only() ? 4 : 6;
154 const ARMSubtarget &Subtarget =
157 if (!Subtarget.isAAPCS_ABI() || Subtarget.isTargetMachO() ||
158 Subtarget.isTargetWindows())
161 const ARMTargetLowering &TLI = *Subtarget.getTargetLowering();
ARMSubtarget.h 1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
106 /// NoARM - True if subtarget does not support ARM mode execution.
121 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
125 /// HasD16 - True if subtarget is limited to 16 double precision
129 /// HasHardwareDivide - True if subtarget supports [su]div
132 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
135 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
139 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
160 /// HasMPExtension - True if the subtarget supports Multiprocessing
164 /// HasVirtualization - True if the subtarget supports the Virtualizatio
    [all...]
  /external/llvm/lib/Target/Sparc/
SparcRegisterInfo.cpp 57 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
68 if (!Subtarget.is64Bit())
79 if (!Subtarget.isV9()) {
92 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
93 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
164 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
167 Subtarget.getStackPointerBias();
174 Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ;
177 if (!Subtarget.isV9() || !Subtarget.hasHardQuad())
    [all...]
CMakeLists.txt 10 tablegen(LLVM SparcGenSubtargetInfo.inc -gen-subtarget)
  /external/llvm/lib/Target/NVPTX/
CMakeLists.txt 8 tablegen(LLVM NVPTXGenSubtargetInfo.inc -gen-subtarget)
  /external/llvm/test/CodeGen/ARM/
minsize-litpools.ll 4 ; CodeGen should be able to set and reset the MinSize subtarget-feature, and
  /external/llvm/lib/Target/Hexagon/
HexagonTargetMachine.h 27 HexagonSubtarget Subtarget;
36 return &Subtarget;
  /external/llvm/include/llvm/Target/
TargetSubtargetInfo.h 10 // This file describes the subtarget options of a Target machine.
84 /// or specific subtarget.
100 /// \brief True if the subtarget should run MachineScheduler after aggressive
112 /// \brief True if the subtarget should enable joining global copies.
118 /// \brief True if the subtarget should run PostMachineScheduler.
125 /// \brief True if the subtarget should run the atomic expansion pass.
158 /// \brief True if the subtarget should run the local reassignment
  /external/llvm/lib/Target/AArch64/
AArch64Subtarget.h 1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
68 /// subtarget initialization.
130 /// subtarget options. Definition of function is auto generated by tblgen.
134 /// how a global value should be referenced for the current subtarget.
140 /// the current subtarget and it is considered prefereable over

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