| /external/llvm/test/CodeGen/AArch64/ |
| arm64-simd-scalar-to-vector.ll | 5 ; CHECK: uaddlv.16b h0, v0
10 ; CHECK-FAST: uaddlv.16b
13 %tmp = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8> %a) nounwind
22 declare i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8>) nounwind readnone
|
| arm64-vaddlv.ll | 19 %vaddlv.i = tail call i64 @llvm.aarch64.neon.uaddlv.i64.v2i32(<2 x i32> %a1) nounwind
23 declare i64 @llvm.aarch64.neon.uaddlv.i64.v2i32(<2 x i32>) nounwind readnone
|
| arm64-popcnt.ll | 10 ; CHECK: uaddlv.8b h0, v0
28 ; CHECK: uaddlv.8b h0, v0
44 ; CHECK: uaddlv.8b h0, v0
|
| arm64-neon-across.ll | 61 declare i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32>)
63 declare i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16>)
65 declare i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8>)
73 declare i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16>)
75 declare i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8>)
100 ; CHECK: uaddlv h{{[0-9]+}}, {{v[0-9]+}}.8b
102 %uaddlvv.i = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8> %a)
109 ; CHECK: uaddlv s{{[0-9]+}}, {{v[0-9]+}}.4h
111 %uaddlvv.i = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16> %a)
142 ; CHECK: uaddlv h{{[0-9]+}}, {{v[0-9]+}}.16
[all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-across.s | 21 uaddlv h0, v1.8b
22 uaddlv h0, v1.16b
23 uaddlv s0, v1.4h
24 uaddlv s0, v1.8h
25 uaddlv d0, v1.4s
27 // CHECK: uaddlv h0, v1.8b // encoding: [0x20,0x38,0x30,0x2e]
28 // CHECK: uaddlv h0, v1.16b // encoding: [0x20,0x38,0x30,0x6e]
29 // CHECK: uaddlv s0, v1.4h // encoding: [0x20,0x38,0x70,0x2e]
30 // CHECK: uaddlv s0, v1.8h // encoding: [0x20,0x38,0x70,0x6e]
31 // CHECK: uaddlv d0, v1.4s // encoding: [0x20,0x38,0xb0,0x6e
[all...] |
| neon-diagnostics.s | [all...] |
| /external/clang/test/CodeGen/ |
| aarch64-neon-across.c | 24 // CHECK: uaddlv {{h[0-9]+}}, {{v[0-9]+}}.8b
30 // CHECK: uaddlv {{s[0-9]+}}, {{v[0-9]+}}.4h
54 // CHECK: uaddlv {{h[0-9]+}}, {{v[0-9]+}}.16b
60 // CHECK: uaddlv {{s[0-9]+}}, {{v[0-9]+}}.8h
66 // CHECK: uaddlv {{d[0-9]+}}, {{v[0-9]+}}.4s
|
| arm64_vadd.c | 15 // CHECK: llvm.aarch64.neon.uaddlv.i64.v2i32
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64SchedCyclone.td | 384 def : InstRW<[CyWriteV3], (instregex "SADDLV","UADDLV")>;
|
| AArch64ISelLowering.cpp | [all...] |
| AArch64InstrInfo.td | [all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | [all...] |
| test-disasm-a64.cc | [all...] |
| test-simulator-a64.cc | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| fp_and_simd.stdout.exp | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/vixl/src/vixl/a64/ |
| macro-assembler-a64.h | [all...] |
| disasm-a64.cc | [all...] |
| simulator-a64.h | [all...] |
| assembler-a64.h | [all...] |
| logic-a64.cc | 1433 LogicVRegister Simulator::uaddlv(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| simulator-a64.cc | [all...] |
| /prebuilts/gcc/darwin-x86/aarch64/aarch64-linux-android-4.9/lib/gcc/aarch64-linux-android/4.9.x-google/include/ |
| arm_neon.h | [all...] |
| /prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9/lib/gcc/aarch64-linux-android/4.9.x-google/include/ |
| arm_neon.h | [all...] |
