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/external/libhevc/common/arm64/
ihevc_inter_pred_filters_luma_vert.s	166 umlsl v19.8h, v0.8b, v22.8b //mul_res1 = vmlsl_u8(mul_res1, src_tmp1, coeffabs_0)// 168 umlsl v19.8h, v2.8b, v24.8b //mul_res1 = vmlsl_u8(mul_res1, src_tmp3, coeffabs_2)// 174 umlsl v19.8h, v5.8b, v27.8b //mul_res1 = vmlsl_u8(mul_res1, src_tmp2, coeffabs_5)// 178 umlsl v19.8h, v7.8b, v29.8b //mul_res1 = vmlsl_u8(mul_res1, src_tmp4, coeffabs_7)// 186 umlsl v20.8h, v1.8b, v22.8b //mul_res2 = vmlsl_u8(mul_res2, src_tmp2, coeffabs_0)// 190 umlsl v20.8h, v3.8b, v24.8b //mul_res2 = vmlsl_u8(mul_res2, src_tmp4, coeffabs_2)// 199 umlsl v20.8h, v6.8b, v27.8b //mul_res2 = vmlsl_u8(mul_res2, src_tmp3, coeffabs_5)// 206 umlsl v20.8h, v16.8b, v29.8b //mul_res2 = vmlsl_u8(mul_res2, src_tmp1, coeffabs_7)// 214 umlsl v21.8h, v2.8b, v22.8b 216 umlsl v21.8h, v4.8b, v24.8     [all...]
ihevc_inter_pred_filters_luma_vert_w16out.s	123 umlsl v19.8h, v0.8b, v22.8b //mul_res1 = vmlsl_u8(mul_res1, src_tmp1, coeffabs_0)// 125 umlsl v19.8h, v2.8b, v24.8b //mul_res1 = vmlsl_u8(mul_res1, src_tmp3, coeffabs_2)// 131 umlsl v19.8h, v5.8b, v27.8b //mul_res1 = vmlsl_u8(mul_res1, src_tmp2, coeffabs_5)// 135 umlsl v19.8h, v7.8b, v29.8b //mul_res1 = vmlsl_u8(mul_res1, src_tmp4, coeffabs_7)// 144 umlsl v20.8h, v1.8b, v22.8b //mul_res2 = vmlsl_u8(mul_res2, src_tmp2, coeffabs_0)// 147 umlsl v20.8h, v3.8b, v24.8b //mul_res2 = vmlsl_u8(mul_res2, src_tmp4, coeffabs_2)// 157 umlsl v20.8h, v6.8b, v27.8b //mul_res2 = vmlsl_u8(mul_res2, src_tmp3, coeffabs_5)// 162 umlsl v20.8h, v16.8b, v29.8b //mul_res2 = vmlsl_u8(mul_res2, src_tmp1, coeffabs_7)// 167 umlsl v21.8h, v2.8b, v22.8b 169 umlsl v21.8h, v4.8b, v24.8     [all...]
ihevc_inter_pred_chroma_vert.s	150 umlsl v6.8h, v5.8b, v0.8b //vmlsl_u8(mul_res1, vreinterpret_u8_u32(src_tmp1), coeffabs_0) 154 umlsl v6.8h, v16.8b, v3.8b 155 umlsl v4.8h, v17.8b, v0.8b 159 umlsl v4.8h, v18.8b, v3.8b 196 umlsl v4.8h, v6.8b, v0.8b 201 umlsl v4.8h, v7.8b, v3.8b 239 umlsl v30.8h, v4.8b, v0.8b 242 umlsl v30.8h, v7.8b, v3.8b 248 umlsl v28.8h, v5.8b, v0.8b 253 umlsl v28.8h, v16.8b, v3.8     [all...]
ihevc_inter_pred_chroma_vert_w16out.s	153 umlsl v6.8h, v5.8b, v0.8b //vmlsl_u8(mul_res1, vreinterpret_u8_u32(src_tmp1), coeffabs_0) 158 umlsl v6.8h, v16.8b, v3.8b 159 umlsl v4.8h, v17.8b, v0.8b 161 umlsl v4.8h, v18.8b, v3.8b 197 umlsl v4.8h, v6.8b, v0.8b 202 umlsl v4.8h, v7.8b, v3.8b 240 umlsl v30.8h, v4.8b, v0.8b 243 umlsl v30.8h, v7.8b, v3.8b 249 umlsl v28.8h, v5.8b, v0.8b 254 umlsl v28.8h, v16.8b, v3.8     [all...]
ihevc_inter_pred_chroma_horz_w16out.s	210 umlsl v30.8h, v0.8b, v24.8b //mul_res = vmlsl_u8(src[0_2], coeffabs_2)// 220 umlsl v30.8h, v6.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)// 229 umlsl v28.8h, v1.8b, v24.8b 235 umlsl v28.8h, v7.8b, v27.8b 267 umlsl v22.8h, v29.8b, v24.8b //mul_res = vmlsl_u8(src[0_2], coeffabs_2)// 282 umlsl v22.8h, v14.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)// 290 umlsl v20.8h, v31.8b, v24.8b //mul_res = vmlsl_u8(src[0_2], coeffabs_2)// 299 umlsl v20.8h, v15.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)// 308 umlsl v30.8h, v0.8b, v24.8b //mul_res = vmlsl_u8(src[0_2], coeffabs_2)// 315 umlsl v30.8h, v6.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)/     [all...]
ihevc_inter_pred_chroma_horz.s	195 umlsl v30.8h, v0.8b, v24.8b //mul_res = vmlsl_u8(src[0_2], coeffabs_2)// 205 umlsl v30.8h, v6.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)// 212 umlsl v28.8h, v1.8b, v24.8b 217 umlsl v28.8h, v7.8b, v27.8b 247 umlsl v22.8h, v29.8b, v24.8b //mul_res = vmlsl_u8(src[0_2], coeffabs_2)// 272 umlsl v22.8h, v14.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)// 281 umlsl v20.8h, v9.8b, v24.8b //mul_res = vmlsl_u8(src[0_2], coeffabs_2)// 292 umlsl v20.8h, v15.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)// 301 umlsl v30.8h, v0.8b, v24.8b //mul_res = vmlsl_u8(src[0_2], coeffabs_2)// 313 umlsl v30.8h, v6.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)/     [all...]
ihevc_inter_pred_filters_luma_horz.s	233 umlsl v8.8h, v0.8b, v24.8b //mul_res = vmlsl_u8(src[0_0], coeffabs_0)// 235 umlsl v8.8h, v2.8b, v26.8b //mul_res = vmlsl_u8(src[0_2], coeffabs_2)// 239 umlsl v8.8h, v5.8b, v29.8b //mul_res = vmlsl_u8(src[0_5], coeffabs_5)// 243 umlsl v8.8h, v7.8b, v31.8b //mul_res = vmlsl_u8(src[0_7], coeffabs_7)// 248 umlsl v10.8h, v14.8b, v26.8b //mul_res = vmlsl_u8(src[0_2], coeffabs_2)// 252 umlsl v10.8h, v17.8b, v29.8b //mul_res = vmlsl_u8(src[0_5], coeffabs_5)// 255 umlsl v10.8h, v19.8b, v31.8b //mul_res = vmlsl_u8(src[0_7], coeffabs_7)// 257 umlsl v10.8h, v12.8b, v24.8b //mul_res = vmlsl_u8(src[0_0], coeffabs_0)// 325 umlsl v8.8h, v0.8b, v24.8b //mul_res = vmlsl_u8(src[0_0], coeffabs_0)// 328 umlsl v8.8h, v4.8b, v26.8b //mul_res = vmlsl_u8(src[0_2], coeffabs_2)/     [all...]
ihevc_inter_pred_luma_horz_w16out.s	277 umlsl v8.8h, v0.8b, v24.8b 278 umlsl v8.8h, v2.8b, v26.8b 281 umlsl v8.8h, v5.8b, v29.8b 283 umlsl v8.8h, v7.8b, v31.8b 341 umlsl v8.8h, v0.8b, v24.8b 343 umlsl v8.8h, v2.8b, v26.8b 349 umlsl v8.8h, v5.8b, v29.8b 352 umlsl v8.8h, v7.8b, v31.8b //store the i iteration result which is in upper part of the register 419 umlsl v8.8h, v0.8b, v24.8b //mul_res = vmlsl_u8(src[0_0], coeffabs_0)// 421 umlsl v8.8h, v2.8b, v26.8b //mul_res = vmlsl_u8(src[0_2], coeffabs_2)/     [all...]
/external/libavc/common/armv8/
ih264_inter_pred_luma_horz_qpel_vert_qpel_av8.s	156 umlsl v24.8h, v2.8b, v31.8b 157 umlsl v24.8h, v8.8b, v31.8b 167 umlsl v28.8h, v19.8b, v31.8b 168 umlsl v28.8h, v22.8b, v31.8b 173 umlsl v24.8h, v3.8b, v31.8b 174 umlsl v24.8h, v9.8b, v31.8b 188 umlsl v24.8h, v19.8b, v31.8b 189 umlsl v24.8h, v22.8b, v31.8b 194 umlsl v16.8h, v4.8b, v31.8b 195 umlsl v16.8h, v10.8b, v31.8     [all...]
ih264_inter_pred_filters_luma_horz_av8.s	155 umlsl v8.8h, v31.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column1,row0) 157 umlsl v10.8h, v30.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column2,row0) 159 umlsl v14.8h, v28.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column1,row1) 161 umlsl v16.8h, v27.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column2,row1) 163 umlsl v8.8h, v31.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column1,row0) 165 umlsl v10.8h, v30.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column2,row0) 167 umlsl v14.8h, v28.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column1,row1) 169 umlsl v16.8h, v27.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column2,row1) 208 umlsl v8.8h, v31.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column1,row2) 210 umlsl v10.8h, v30.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column2,row2     [all...]
ih264_inter_pred_luma_horz_qpel_av8.s	163 umlsl v8.8h, v31.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column1,row0) 165 umlsl v10.8h, v30.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column2,row0) 167 umlsl v14.8h, v28.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column1,row1) 169 umlsl v16.8h, v27.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column2,row1) 171 umlsl v8.8h, v31.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column1,row0) 173 umlsl v10.8h, v30.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column2,row0) 175 umlsl v14.8h, v28.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column1,row1) 177 umlsl v16.8h, v27.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column2,row1) 224 umlsl v8.8h, v31.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column1,row2) 226 umlsl v10.8h, v30.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column2,row2     [all...]
/frameworks/rs/cpu_ref/
rsCpuIntrinsics_advsimd_3DLUT.S	40 umlsl v12.8h, v16.8b, v8.8b 41 umlsl v13.8h, v17.8b, v9.8b 57 umlsl v14.8h, v16.8b, v8.8b 58 umlsl v15.8h, v17.8b, v9.8b 65 umlsl v8.4s, v12.4h, \zr0 75 umlsl v8.4s, v13.4h, \zr1 85 umlsl v8.4s, v10.4h, \xr0 86 umlsl v9.4s, v11.4h, \xr1
rsCpuIntrinsics_advsimd_Resize.S	62 umlsl v12.4s, v8.4h, v3.h[0] 66 umlsl v12.4s, v11.4h, v3.h[3] 89 umlsl v12.4s, v8.4h, v3.h[0] 91 umlsl v12.4s, v11.4h, v3.h[3]
/external/libavc/encoder/armv8/
ih264e_half_pel_av8.s	147 umlsl v8.8h, v31.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column1,row0) 149 umlsl v10.8h, v30.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column2,row0) 151 umlsl v12.8h, v29.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column3,row0) 153 umlsl v14.8h, v28.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column1,row1) 156 umlsl v16.8h, v27.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column2,row1) 158 umlsl v18.8h, v26.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column3,row1) 160 umlsl v8.8h, v31.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column1,row0) 162 umlsl v10.8h, v30.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column2,row0) 164 umlsl v12.8h, v29.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column3,row0) 166 umlsl v14.8h, v28.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column1,row1     [all...]
/external/llvm/test/MC/AArch64/
neon-2velem.s	133 umlsl v0.4s, v1.4h, v2.h[2] 134 umlsl v0.2d, v1.2s, v2.s[2] 135 umlsl v0.2d, v1.2s, v22.s[2] 140 // CHECK: umlsl v0.4s, v1.4h, v2.h[2] // encoding: [0x20,0x60,0x62,0x2f] 141 // CHECK: umlsl v0.2d, v1.2s, v2.s[2] // encoding: [0x20,0x68,0x82,0x2f] 142 // CHECK: umlsl v0.2d, v1.2s, v22.s[2] // encoding: [0x20,0x68,0x96,0x2f]
neon-3vdiff.s	193 umlsl v0.8h, v1.8b, v2.8b 194 umlsl v0.4s, v1.4h, v2.4h 195 umlsl v0.2d, v1.2s, v2.2s 197 // CHECK: umlsl v0.8h, v1.8b, v2.8b // encoding: [0x20,0xa0,0x22,0x2e] 198 // CHECK: umlsl v0.4s, v1.4h, v2.4h // encoding: [0x20,0xa0,0x62,0x2e] 199 // CHECK: umlsl v0.2d, v1.2s, v2.2s // encoding: [0x20,0xa0,0xa2,0x2e]
neon-diagnostics.s	[all...]
/external/llvm/test/CodeGen/AArch64/
aarch64-smull.ll	188 ; CHECK: umlsl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 201 ; CHECK: umlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 214 ; CHECK: umlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
/external/clang/test/CodeGen/
aarch64-neon-2velem.c	443 // CHECK: umlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3] 449 // CHECK: umlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1] 455 // CHECK: umlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7] 461 // CHECK: umlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]     [all...]
/external/vixl/doc/
supported-instructions.md	[all...]
/external/vixl/src/vixl/a64/
macro-assembler-a64.h	[all...]
logic-a64.cc	983 LogicVRegister Simulator::umlsl(VectorFormat vform, function in class:vixl::Simulator 3109 LogicVRegister Simulator::umlsl(VectorFormat vform, function in class:vixl::Simulator     [all...]
/external/valgrind/none/tests/arm64/
fp_and_simd.c	[all...]
/external/llvm/lib/Target/AArch64/
AArch64SchedCyclone.td	522 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
/external/vixl/test/
test-simulator-traces-a64.h	[all...]

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