| /external/llvm/test/MC/AArch64/ |
| neon-shift.s | 28 ushl v0.8b, v1.8b, v2.8b
29 ushl v0.16b, v1.16b, v2.16b
30 ushl v0.4h, v1.4h, v2.4h
31 ushl v0.8h, v1.8h, v2.8h
32 ushl v0.2s, v1.2s, v2.2s
33 ushl v0.4s, v1.4s, v2.4s
34 ushl v0.2d, v1.2d, v2.2d
36 // CHECK: ushl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x44,0x22,0x2e]
37 // CHECK: ushl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x44,0x22,0x6e]
38 // CHECK: ushl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x44,0x62,0x2e
[all...] |
| neon-scalar-shift.s | 13 ushl d17, d31, d8
15 // CHECK: ushl d17, d31, d8 // encoding: [0xf1,0x47,0xe8,0x7e]
|
| arm64-advsimd.s | 370 ushl.8b v0, v0, v0
441 ; CHECK: ushl.8b v0, v0, v0 ; encoding: [0x00,0x44,0x20,0x2e]
[all...] |
| neon-diagnostics.s | [all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vshr.ll | 37 ; CHECK-NEXT: ushl.8h [[REG6:v[0-9]+]], [[REG6]], [[REG5]]
|
| /external/libavc/common/armv8/ |
| ih264_resi_trans_quant_av8.s | 586 ushl v14.4s, v14.4s, v22.4s
587 ushl v15.4s, v15.4s, v22.4s
588 ushl v16.4s, v16.4s, v22.4s
589 ushl v17.4s, v17.4s, v22.4s
698 ushl v2.4s, v25.4s, v24.4s //>>qbit
699 ushl v3.4s, v26.4s, v24.4s //>>qbit
|
| /external/clang/test/CodeGen/ |
| arm64-scalar-test.c | 156 // CHECK: ushl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
| aarch64-neon-intrinsics.c | [all...] |
| /external/vixl/src/vixl/a64/ |
| simulator-a64.cc | [all...] |
| logic-a64.cc | 1919 LogicVRegister Simulator::ushl(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| disasm-a64.cc | [all...] |
| macro-assembler-a64.h | [all...] |
| simulator-a64.h | [all...] |
| assembler-a64.h | [all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | [all...] |
| test-simulator-a64.cc | [all...] |
| test-disasm-a64.cc | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64SchedCyclone.td | 484 // SSHL,USHL are WriteV.
|
| AArch64InstrInfo.td | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| /external/deqp/modules/gles3/functional/ |
| es3fShaderPrecisionTests.cpp | 197 // in fp/vector registers it uses USHL that selects shift direction
[all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/valgrind/VEX/priv/ |
| host_arm64_defs.c | 683 case ARM64vecb_USHL64x2: *nm = "ushl "; *ar = "2d"; return;
684 case ARM64vecb_USHL32x4: *nm = "ushl "; *ar = "4s"; return;
685 case ARM64vecb_USHL16x8: *nm = "ushl "; *ar = "8h"; return;
686 case ARM64vecb_USHL8x16: *nm = "ushl "; *ar = "16b"; return;
[all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| neon-instructions.txt | 383 # CHECK: ushl v10.16b, v5.16b, v2.16b
385 # CHECK: ushl v10.8h, v5.8h, v2.8h
387 # CHECK: ushl v10.4s, v5.4s, v2.4s
455 # CHECK: ushl d0, d0, d0
[all...] |
| arm64-advsimd.txt | 353 # CHECK: ushl.8b v0, v0, v0
[all...] |
