| /external/llvm/test/CodeGen/AArch64/ |
| arm64-subvector-extend.ll | 11 ; CHECK-NEXT: ushll.8h v0, v0, #0
28 ; CHECK-NEXT: ushll.8h v0, v0, #0
49 ; CHECK-NEXT: ushll.4s v0, v0, #0
66 ; CHECK-NEXT: ushll.4s v0, v0, #0
83 ; CHECK-NEXT: ushll.8h v0, v0, #0
85 ; CHECK-NEXT: ushll.4s v0, v0, #0
108 ; CHECK-NEXT: ushll.2d v0, v0, #0
125 ; CHECK-NEXT: ushll.4s v0, v0, #0
127 ; CHECK-NEXT: ushll.2d v0, v0, #0
|
| arm64-extend-int-to-fp.ll | 5 ; CHECK: ushll.4s v0, v0, #0
|
| arm64-vector-ext.ll | 4 ;CHECK: ushll.4s v0, v0, #0
|
| arm64-vselect.ll | 7 ; ushll.4s v0, v0, #0
|
| complex-int-to-fp.ll | 24 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], v0, #0
45 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
66 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
139 ; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
159 ; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
|
| arm64-vbitwise.ll | 32 ;CHECK: ushll.8h
48 ;CHECK: ushll.4s
64 ;CHECK: ushll.2d
|
| neon-shift-left-long.ll | 29 ; CHECK: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #3
37 ; CHECK: ushll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #9
45 ; CHECK: ushll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #19
128 ; CHECK: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
135 ; CHECK: ushll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #0
142 ; CHECK: ushll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #0
198 ; CHECK-NEXT: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
|
| fp16-v8-instructions.ll | 311 ; CHECK-NEXT: ushll v[[REG1:[0-9]+]].8h, v0.8b, #0
313 ; CHECK-NEXT: ushll [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
327 ; CHECK-NEXT: ushll [[HI:v[0-9]+\.4s]], v0.4h, #0
|
| fp16-v4-instructions.ll | 181 ; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
192 ; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
|
| arm64-vshift.ll | [all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-shift-left-long.s | 25 ushll v0.8h, v1.8b, #3
26 ushll v0.4s, v1.4h, #3
27 ushll v0.2d, v1.2s, #3
32 // CHECK: ushll v0.8h, v1.8b, #3 // encoding: [0x20,0xa4,0x0b,0x2f]
33 // CHECK: ushll v0.4s, v1.4h, #3 // encoding: [0x20,0xa4,0x13,0x2f]
34 // CHECK: ushll v0.2d, v1.2s, #3 // encoding: [0x20,0xa4,0x23,0x2f]
|
| neon-uxtl.s | 12 // CHECK: ushll v0.8h, v1.8b, #0 // encoding: [0x20,0xa4,0x08,0x2f]
13 // CHECK: ushll v0.4s, v1.4h, #0 // encoding: [0x20,0xa4,0x10,0x2f]
14 // CHECK: ushll v0.2d, v1.2s, #0 // encoding: [0x20,0xa4,0x20,0x2f]
|
| arm64-aliases.s | 708 ; CHECK: ushll.8h v1, v2, #0
710 ; CHECK: ushll.8h v1, v2, #0
713 ; CHECK: ushll.4s v1, v2, #0
715 ; CHECK: ushll.4s v1, v2, #0
718 ; CHECK: ushll.2d v1, v2, #0
720 ; CHECK: ushll.2d v1, v2, #0
|
| arm64-advsimd.s | [all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_3DLUT.S | 63 ushll v8.4s, v12.4h, #8
73 ushll v8.4s, v13.4h, #8
83 ushll v8.4s, v10.4h, #8
84 ushll v9.4s, v11.4h, #8
175 ushll v6.4s, v12.4h, #2
|
| rsCpuIntrinsics_advsimd_YuvToRGB.S | 82 ushll v19.8h, \regu\().8b, #2
|
| /external/libavc/common/armv8/ |
| ih264_deblk_luma_av8.s | 159 ushll v26.8h, v9.8b, #1 //
161 ushll v16.8h, v8.8b, #1 //Q13,Q8 = (p1<<1)
165 ushll v16.8h, v2.8b, #1 //
166 ushll v26.8h, v3.8b, #1 //Q13,Q8 = (q1<<1)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64SchedCyclone.td | 493 // SHLL,SSHLL,USHLL
|
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | [all...] |
| /external/vixl/test/ |
| test-disasm-a64.cc | [all...] |
| test-simulator-traces-a64.h | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/vixl/src/vixl/a64/ |
| disasm-a64.cc | [all...] |
| macro-assembler-a64.h | [all...] |
