| /external/llvm/test/MC/AArch64/ |
| neon-shift-left-long.s | 28 ushll2 v0.8h, v1.16b, #3
29 ushll2 v0.4s, v1.8h, #3
30 ushll2 v0.2d, v1.4s, #3
35 // CHECK: ushll2 v0.8h, v1.16b, #3 // encoding: [0x20,0xa4,0x0b,0x6f]
36 // CHECK: ushll2 v0.4s, v1.8h, #3 // encoding: [0x20,0xa4,0x13,0x6f]
37 // CHECK: ushll2 v0.2d, v1.4s, #3 // encoding: [0x20,0xa4,0x23,0x6f]
|
| neon-uxtl.s | 24 // CHECK: ushll2 v0.8h, v1.16b, #0 // encoding: [0x20,0xa4,0x08,0x6f]
25 // CHECK: ushll2 v0.4s, v1.8h, #0 // encoding: [0x20,0xa4,0x10,0x6f]
26 // CHECK: ushll2 v0.2d, v1.4s, #0 // encoding: [0x20,0xa4,0x20,0x6f]
|
| arm64-aliases.s | 723 ; CHECK: ushll2.8h v1, v2, #0
725 ; CHECK: ushll2.8h v1, v2, #0
728 ; CHECK: ushll2.4s v1, v2, #0
730 ; CHECK: ushll2.4s v1, v2, #0
733 ; CHECK: ushll2.2d v1, v2, #0
735 ; CHECK: ushll2.2d v1, v2, #0
|
| arm64-advsimd.s | [all...] |
| neon-diagnostics.s | [all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-subvector-extend.ll | 27 ; CHECK-NEXT: ushll2.8h v1, v0, #0
65 ; CHECK-NEXT: ushll2.4s v1, v0, #0
84 ; CHECK-NEXT: ushll2.4s v1, v0, #0
107 ; CHECK-NEXT: ushll2.2d v1, v0, #0
126 ; CHECK-NEXT: ushll2.2d v1, v0, #0
|
| neon-shift-left-long.ll | 80 ; CHECK: ushll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #3
89 ; CHECK: ushll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #9
98 ; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #19
173 ; CHECK: ushll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #0
181 ; CHECK: ushll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #0
189 ; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #0
|
| fp16-v8-instructions.ll | 312 ; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
326 ; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
|
| arm64-vshift.ll | [all...] |
| /external/clang/test/CodeGen/ |
| arm64_neon_high_half.c | 172 // CHECK: ushll2.8h
177 // CHECK: ushll2.4s
182 // CHECK: ushll2.2d
|
| aarch64-neon-intrinsics.c | [all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_3DLUT.S | 64 ushll2 v9.4s, v12.8h, #8
74 ushll2 v9.4s, v13.8h, #8
176 ushll2 v7.4s, v12.8h, #2
|
| rsCpuIntrinsics_advsimd_YuvToRGB.S | 83 ushll2 v23.8h, \regu\().16b, #2
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| /external/vixl/test/ |
| test-disasm-a64.cc | [all...] |
| test-simulator-traces-a64.h | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/vixl/src/vixl/a64/ |
| macro-assembler-a64.h | [all...] |
| assembler-a64.cc | [all...] |
| disasm-a64.cc | [all...] |
| simulator-a64.h | [all...] |
| assembler-a64.h | [all...] |
| logic-a64.cc | 1664 LogicVRegister Simulator::ushll2(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| simulator-a64.cc | [all...] |
