| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vsra.ll | 75 ;CHECK: usra.8b
85 ;CHECK: usra.4h
95 ;CHECK: usra.2s
106 ;CHECK: usra.16b
116 ;CHECK: usra.8h
126 ;CHECK: usra.4s
136 ;CHECK: usra.2d
|
| arm64-neon-simd-shift.ll | 159 ; CHECK: usra {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #3
167 ; CHECK: usra {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #3
175 ; CHECK: usra {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #3
183 ; CHECK: usra {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #3
191 ; CHECK: usra {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #3
199 ; CHECK: usra {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #3
207 ; CHECK: usra {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #3
|
| arm64-vshift.ll | [all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-simd-shift.s | 64 usra v0.8b, v1.8b, #3
65 usra v0.4h, v1.4h, #3
66 usra v0.2s, v1.2s, #3
67 usra v0.16b, v1.16b, #3
68 usra v0.8h, v1.8h, #3
69 usra v0.4s, v1.4s, #3
70 usra v0.2d, v1.2d, #3
72 // CHECK: usra v0.8b, v1.8b, #3 // encoding: [0x20,0x14,0x0d,0x2f]
73 // CHECK: usra v0.4h, v1.4h, #3 // encoding: [0x20,0x14,0x1d,0x2f]
74 // CHECK: usra v0.2s, v1.2s, #3 // encoding: [0x20,0x14,0x3d,0x2f
[all...] |
| arm64-advsimd.s | [all...] |
| neon-scalar-shift-imm.s | 43 usra d20, d13, #61
45 // CHECK: usra d20, d13, #61 // encoding: [0xb4,0x15,0x43,0x7f]
|
| neon-diagnostics.s | [all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_3DLUT.S | 160 usra v0.8h, v0.8h, #8
161 usra v1.8h, v1.8h, #8
162 usra v2.8h, v2.8h, #8
|
| /external/vixl/test/ |
| test-disasm-a64.cc | [all...] |
| test-simulator-traces-a64.h | [all...] |
| test-simulator-a64.cc | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | [all...] |
| neon-instructions.txt | 774 # CHECK: usra v0.8b, v1.8b, #3
775 # CHECK: usra v0.4h, v1.4h, #3
776 # CHECK: usra v0.2s, v1.2s, #3
777 # CHECK: usra v0.16b, v1.16b, #3
778 # CHECK: usra v0.8h, v1.8h, #3
779 # CHECK: usra v0.4s, v1.4s, #3
780 # CHECK: usra v0.2d, v1.2d, #3
[all...] |
| /external/clang/test/CodeGen/ |
| aarch64-neon-intrinsics.c | [all...] |
| /external/libavc/common/armv8/ |
| ih264_deblk_luma_av8.s | 274 usra v20.16b, v0.16b, #2 //alpha >>2 +2
[all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/vixl/src/vixl/a64/ |
| disasm-a64.cc | [all...] |
| macro-assembler-a64.h | [all...] |
| simulator-a64.cc | [all...] |
| simulator-a64.h | [all...] |
| assembler-a64.h | [all...] |
| logic-a64.cc | 1784 LogicVRegister Simulator::usra(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| assembler-a64.cc | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.td | [all...] |
