/external/llvm/lib/Target/X86/ |
X86ScheduleSLM.td | 63 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; } 67 def : WriteRes<SchedRW.Folded, [MEC_RSV, ExePort]> { 74 def : WriteRes<WriteRMW, [MEC_RSV]>; 76 def : WriteRes<WriteStore, [IEC_RSV01, MEC_RSV]>; 77 def : WriteRes<WriteLoad, [MEC_RSV]> { let Latency = 3; } 78 def : WriteRes<WriteMove, [IEC_RSV01]>; 79 def : WriteRes<WriteZero, []>; 89 def : WriteRes<WriteLEA, [IEC_RSV1]>; 92 def : WriteRes<WriteIDiv, [IEC_RSV01, SMDivider]> { 96 def : WriteRes<WriteIDivLd, [MEC_RSV, IEC_RSV01, SMDivider]> [all...] |
X86ScheduleBtVer2.td | 81 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; } 85 def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> { 94 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; } 98 def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> { 104 def : WriteRes<WriteRMW, [JSAGU]>; 113 def : WriteRes<WriteIMulH, [JALU1]> { 119 def : WriteRes<WriteIDiv, [JALU1, JDiv]> { 123 def : WriteRes<WriteIDivLd, [JALU1, JLAGU, JDiv]> { 130 def : WriteRes<WriteLEA, [JALU01]>; 143 def : WriteRes<WriteLoad, [JLAGU]> { let Latency = 5; [all...] |
X86SchedSandyBridge.td | 76 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; } 80 def : WriteRes<SchedRW.Folded, [SBPort23, ExePort]> { 87 def : WriteRes<WriteRMW, [SBPort4]>; 89 def : WriteRes<WriteStore, [SBPort23, SBPort4]>; 90 def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 4; } 91 def : WriteRes<WriteMove, [SBPort015]>; 92 def : WriteRes<WriteZero, []>; 96 def : WriteRes<WriteIMulH, []> { let Latency = 3; } 103 def : WriteRes<WriteLEA, [SBPort15]>; 106 def : WriteRes<WriteIDiv, [SBPort0, SBDivider]> [all...] |
X86SchedHaswell.td | 86 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; } 90 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> { 97 def : WriteRes<WriteRMW, [HWPort4]>; 101 def : WriteRes<WriteStore, [HWPort237, HWPort4]>; 102 def : WriteRes<WriteLoad, [HWPort23]> { let Latency = 4; } 103 def : WriteRes<WriteMove, [HWPort0156]>; 104 def : WriteRes<WriteZero, []>; 108 def : WriteRes<WriteIMulH, []> { let Latency = 3; } 115 def : WriteRes<WriteLEA, [HWPort15]>; 118 def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64SchedA53.td | 57 def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; } 58 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; } 59 def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 3; } 60 def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 3; } 61 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; } 62 def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; } 65 def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; } 66 def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; } 69 def : WriteRes<WriteID32, [A53UnitDiv]> { let Latency = 4; } 70 def : WriteRes<WriteID64, [A53UnitDiv]> { let Latency = 4; [all...] |
AArch64SchedCyclone.td | 129 def : WriteRes<WriteImm, [CyUnitI]>; 148 def : WriteRes<WriteI, [CyUnitI]>; 154 def : WriteRes<WriteISReg, [CyUnitIS]> { 162 def : WriteRes<WriteIEReg, [CyUnitIS]> { 169 def : WriteRes<WriteIS, [CyUnitIS]>; 174 def : WriteRes<WriteExtr, [CyUnitIS, CyUnitIS]> { 190 def : WriteRes<WriteIM32, [CyUnitIM]> { 194 def : WriteRes<WriteIM64, [CyUnitIM]> { 205 def : WriteRes<WriteID32, [CyUnitID, CyUnitIntDiv]> { 212 def : WriteRes<WriteID64, [CyUnitID, CyUnitIntDiv]> [all...] |
AArch64SchedA57.td | 61 // defining the aliases precludes the need for mapping them using WriteRes. The 78 def : WriteRes<WriteIM32, [A57UnitM]> { let Latency = 3; } 79 def : WriteRes<WriteIM64, [A57UnitM]> { let Latency = 5; } 99 def : WriteRes<WriteSys, []> { let Latency = 1; } 100 def : WriteRes<WriteBarrier, []> { let Latency = 1; } 101 def : WriteRes<WriteHint, []> { let Latency = 1; } 103 def : WriteRes<WriteLDHi, []> { let Latency = 4; } [all...] |
/libcore/harmony-tests/src/test/java/org/apache/harmony/tests/java/nio/channels/ |
ChannelsTest.java | 180 int writeres = this.testNum; local 188 writeres = rbChannel.write(writebuf); 189 assertEquals(0, writeres); 192 writeres = rbChannel.write(writebuf); 200 int writeres = this.testNum; local 210 writeres = rbChannel.write(writebuf); 215 assertEquals(this.testNum, writeres);
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DatagramChannelTest.java | 218 long writeres = 0; local 219 writeres = testMock.write(readBuf); 221 assertEquals(0, writeres); 222 writeres = testMocknull.write(readBuf); 223 assertEquals(0, writeres); [all...] |
/external/llvm/lib/Target/R600/ |
SISchedule.td | 47 int latency> : WriteRes<write, resources> {
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/external/llvm/utils/TableGen/ |
SubtargetEmitter.cpp | 657 // Find the WriteRes Record that defines processor resources for this 690 if (!(*WRI)->isSubClassOf("WriteRes")) [all...] |
CodeGenSchedule.cpp | [all...] |
/external/llvm/include/llvm/Target/ |
TargetSchedule.td | 27 // each subtarget, define WriteRes and ReadAdvance to associate 128 // specified in WriteRes expire. Setting BufferSize=1 changes this to 230 // Define values common to WriteRes and SchedWriteRes. 280 class WriteRes<SchedWrite write, list<ProcResourceKind> resources>
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/external/llvm/lib/Target/ARM/ |
ARMScheduleSwift.td | [all...] |
ARMScheduleA9.td | [all...] |
ARMSchedule.td | 48 // def : WriteRes<WriteALUsr, [P01, P01]> {
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