1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark (at) gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25 #ifndef __MSM_DRM_H__ 26 #define __MSM_DRM_H__ 27 28 #include <stddef.h> 29 #include "drm.h" 30 31 /* Please note that modifications to all structs defined here are 32 * subject to backwards-compatibility constraints: 33 * 1) Do not use pointers, use uint64_t instead for 32 bit / 64 bit 34 * user/kernel compatibility 35 * 2) Keep fields aligned to their size 36 * 3) Because of how drm_ioctl() works, we can add new fields at 37 * the end of an ioctl if some care is taken: drm_ioctl() will 38 * zero out the new fields at the tail of the ioctl, so a zero 39 * value should have a backwards compatible meaning. And for 40 * output params, userspace won't see the newly added output 41 * fields.. so that has to be somehow ok. 42 */ 43 44 #define MSM_PIPE_NONE 0x00 45 #define MSM_PIPE_2D0 0x01 46 #define MSM_PIPE_2D1 0x02 47 #define MSM_PIPE_3D0 0x10 48 49 /* timeouts are specified in clock-monotonic absolute times (to simplify 50 * restarting interrupted ioctls). The following struct is logically the 51 * same as 'struct timespec' but 32/64b ABI safe. 52 */ 53 struct drm_msm_timespec { 54 int64_t tv_sec; /* seconds */ 55 int64_t tv_nsec; /* nanoseconds */ 56 }; 57 58 #define MSM_PARAM_GPU_ID 0x01 59 #define MSM_PARAM_GMEM_SIZE 0x02 60 #define MSM_PARAM_CHIP_ID 0x03 61 62 struct drm_msm_param { 63 uint32_t pipe; /* in, MSM_PIPE_x */ 64 uint32_t param; /* in, MSM_PARAM_x */ 65 uint64_t value; /* out (get_param) or in (set_param) */ 66 }; 67 68 /* 69 * GEM buffers: 70 */ 71 72 #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */ 73 #define MSM_BO_GPU_READONLY 0x00000002 74 #define MSM_BO_CACHE_MASK 0x000f0000 75 /* cache modes */ 76 #define MSM_BO_CACHED 0x00010000 77 #define MSM_BO_WC 0x00020000 78 #define MSM_BO_UNCACHED 0x00040000 79 80 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \ 81 MSM_BO_GPU_READONLY | \ 82 MSM_BO_CACHED | \ 83 MSM_BO_WC | \ 84 MSM_BO_UNCACHED) 85 86 struct drm_msm_gem_new { 87 uint64_t size; /* in */ 88 uint32_t flags; /* in, mask of MSM_BO_x */ 89 uint32_t handle; /* out */ 90 }; 91 92 struct drm_msm_gem_info { 93 uint32_t handle; /* in */ 94 uint32_t pad; 95 uint64_t offset; /* out, offset to pass to mmap() */ 96 }; 97 98 #define MSM_PREP_READ 0x01 99 #define MSM_PREP_WRITE 0x02 100 #define MSM_PREP_NOSYNC 0x04 101 102 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 103 104 struct drm_msm_gem_cpu_prep { 105 uint32_t handle; /* in */ 106 uint32_t op; /* in, mask of MSM_PREP_x */ 107 struct drm_msm_timespec timeout; /* in */ 108 }; 109 110 struct drm_msm_gem_cpu_fini { 111 uint32_t handle; /* in */ 112 }; 113 114 /* 115 * Cmdstream Submission: 116 */ 117 118 /* The value written into the cmdstream is logically: 119 * 120 * ((relocbuf->gpuaddr + reloc_offset) << shift) | or 121 * 122 * When we have GPU's w/ >32bit ptrs, it should be possible to deal 123 * with this by emit'ing two reloc entries with appropriate shift 124 * values. Or a new MSM_SUBMIT_CMD_x type would also be an option. 125 * 126 * NOTE that reloc's must be sorted by order of increasing submit_offset, 127 * otherwise EINVAL. 128 */ 129 struct drm_msm_gem_submit_reloc { 130 uint32_t submit_offset; /* in, offset from submit_bo */ 131 uint32_t or; /* in, value OR'd with result */ 132 int32_t shift; /* in, amount of left shift (can be negative) */ 133 uint32_t reloc_idx; /* in, index of reloc_bo buffer */ 134 uint64_t reloc_offset; /* in, offset from start of reloc_bo */ 135 }; 136 137 /* submit-types: 138 * BUF - this cmd buffer is executed normally. 139 * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are 140 * processed normally, but the kernel does not setup an IB to 141 * this buffer in the first-level ringbuffer 142 * CTX_RESTORE_BUF - only executed if there has been a GPU context 143 * switch since the last SUBMIT ioctl 144 */ 145 #define MSM_SUBMIT_CMD_BUF 0x0001 146 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 147 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 148 struct drm_msm_gem_submit_cmd { 149 uint32_t type; /* in, one of MSM_SUBMIT_CMD_x */ 150 uint32_t submit_idx; /* in, index of submit_bo cmdstream buffer */ 151 uint32_t submit_offset; /* in, offset into submit_bo */ 152 uint32_t size; /* in, cmdstream size */ 153 uint32_t pad; 154 uint32_t nr_relocs; /* in, number of submit_reloc's */ 155 uint64_t __user relocs; /* in, ptr to array of submit_reloc's */ 156 }; 157 158 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the 159 * cmdstream buffer(s) themselves or reloc entries) has one (and only 160 * one) entry in the submit->bos[] table. 161 * 162 * As a optimization, the current buffer (gpu virtual address) can be 163 * passed back through the 'presumed' field. If on a subsequent reloc, 164 * userspace passes back a 'presumed' address that is still valid, 165 * then patching the cmdstream for this entry is skipped. This can 166 * avoid kernel needing to map/access the cmdstream bo in the common 167 * case. 168 */ 169 #define MSM_SUBMIT_BO_READ 0x0001 170 #define MSM_SUBMIT_BO_WRITE 0x0002 171 172 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) 173 174 struct drm_msm_gem_submit_bo { 175 uint32_t flags; /* in, mask of MSM_SUBMIT_BO_x */ 176 uint32_t handle; /* in, GEM handle */ 177 uint64_t presumed; /* in/out, presumed buffer address */ 178 }; 179 180 /* Each cmdstream submit consists of a table of buffers involved, and 181 * one or more cmdstream buffers. This allows for conditional execution 182 * (context-restore), and IB buffers needed for per tile/bin draw cmds. 183 */ 184 struct drm_msm_gem_submit { 185 uint32_t pipe; /* in, MSM_PIPE_x */ 186 uint32_t fence; /* out */ 187 uint32_t nr_bos; /* in, number of submit_bo's */ 188 uint32_t nr_cmds; /* in, number of submit_cmd's */ 189 uint64_t __user bos; /* in, ptr to array of submit_bo's */ 190 uint64_t __user cmds; /* in, ptr to array of submit_cmd's */ 191 }; 192 193 /* The normal way to synchronize with the GPU is just to CPU_PREP on 194 * a buffer if you need to access it from the CPU (other cmdstream 195 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all 196 * handle the required synchronization under the hood). This ioctl 197 * mainly just exists as a way to implement the gallium pipe_fence 198 * APIs without requiring a dummy bo to synchronize on. 199 */ 200 struct drm_msm_wait_fence { 201 uint32_t fence; /* in */ 202 uint32_t pad; 203 struct drm_msm_timespec timeout; /* in */ 204 }; 205 206 #define DRM_MSM_GET_PARAM 0x00 207 /* placeholder: 208 #define DRM_MSM_SET_PARAM 0x01 209 */ 210 #define DRM_MSM_GEM_NEW 0x02 211 #define DRM_MSM_GEM_INFO 0x03 212 #define DRM_MSM_GEM_CPU_PREP 0x04 213 #define DRM_MSM_GEM_CPU_FINI 0x05 214 #define DRM_MSM_GEM_SUBMIT 0x06 215 #define DRM_MSM_WAIT_FENCE 0x07 216 #define DRM_MSM_NUM_IOCTLS 0x08 217 218 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 219 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 220 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 221 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 222 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 223 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 224 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 225 226 #endif /* __MSM_DRM_H__ */ 227
