1 /* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef __NOUVEAU_DRM_H__ 26 #define __NOUVEAU_DRM_H__ 27 28 #define NOUVEAU_DRM_HEADER_PATCHLEVEL 16 29 30 struct drm_nouveau_channel_alloc { 31 uint32_t fb_ctxdma_handle; 32 uint32_t tt_ctxdma_handle; 33 34 int channel; 35 uint32_t pushbuf_domains; 36 37 /* Notifier memory */ 38 uint32_t notifier_handle; 39 40 /* DRM-enforced subchannel assignments */ 41 struct { 42 uint32_t handle; 43 uint32_t grclass; 44 } subchan[8]; 45 uint32_t nr_subchan; 46 }; 47 48 struct drm_nouveau_channel_free { 49 int channel; 50 }; 51 52 struct drm_nouveau_grobj_alloc { 53 int channel; 54 uint32_t handle; 55 int class; 56 }; 57 58 struct drm_nouveau_notifierobj_alloc { 59 uint32_t channel; 60 uint32_t handle; 61 uint32_t size; 62 uint32_t offset; 63 }; 64 65 struct drm_nouveau_gpuobj_free { 66 int channel; 67 uint32_t handle; 68 }; 69 70 /* FIXME : maybe unify {GET,SET}PARAMs */ 71 #define NOUVEAU_GETPARAM_PCI_VENDOR 3 72 #define NOUVEAU_GETPARAM_PCI_DEVICE 4 73 #define NOUVEAU_GETPARAM_BUS_TYPE 5 74 #define NOUVEAU_GETPARAM_FB_PHYSICAL 6 75 #define NOUVEAU_GETPARAM_AGP_PHYSICAL 7 76 #define NOUVEAU_GETPARAM_FB_SIZE 8 77 #define NOUVEAU_GETPARAM_AGP_SIZE 9 78 #define NOUVEAU_GETPARAM_PCI_PHYSICAL 10 79 #define NOUVEAU_GETPARAM_CHIPSET_ID 11 80 #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 81 #define NOUVEAU_GETPARAM_GRAPH_UNITS 13 82 #define NOUVEAU_GETPARAM_PTIMER_TIME 14 83 #define NOUVEAU_GETPARAM_HAS_BO_USAGE 15 84 #define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16 85 struct drm_nouveau_getparam { 86 uint64_t param; 87 uint64_t value; 88 }; 89 90 struct drm_nouveau_setparam { 91 uint64_t param; 92 uint64_t value; 93 }; 94 95 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) 96 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) 97 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) 98 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) 99 100 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 101 #define NOUVEAU_GEM_TILE_16BPP 0x00000001 102 #define NOUVEAU_GEM_TILE_32BPP 0x00000002 103 #define NOUVEAU_GEM_TILE_ZETA 0x00000004 104 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 105 106 struct drm_nouveau_gem_info { 107 uint32_t handle; 108 uint32_t domain; 109 uint64_t size; 110 uint64_t offset; 111 uint64_t map_handle; 112 uint32_t tile_mode; 113 uint32_t tile_flags; 114 }; 115 116 struct drm_nouveau_gem_new { 117 struct drm_nouveau_gem_info info; 118 uint32_t channel_hint; 119 uint32_t align; 120 }; 121 122 #define NOUVEAU_GEM_MAX_BUFFERS 1024 123 struct drm_nouveau_gem_pushbuf_bo_presumed { 124 uint32_t valid; 125 uint32_t domain; 126 uint64_t offset; 127 }; 128 129 struct drm_nouveau_gem_pushbuf_bo { 130 uint64_t user_priv; 131 uint32_t handle; 132 uint32_t read_domains; 133 uint32_t write_domains; 134 uint32_t valid_domains; 135 struct drm_nouveau_gem_pushbuf_bo_presumed presumed; 136 }; 137 138 #define NOUVEAU_GEM_RELOC_LOW (1 << 0) 139 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1) 140 #define NOUVEAU_GEM_RELOC_OR (1 << 2) 141 #define NOUVEAU_GEM_MAX_RELOCS 1024 142 struct drm_nouveau_gem_pushbuf_reloc { 143 uint32_t reloc_bo_index; 144 uint32_t reloc_bo_offset; 145 uint32_t bo_index; 146 uint32_t flags; 147 uint32_t data; 148 uint32_t vor; 149 uint32_t tor; 150 }; 151 152 #define NOUVEAU_GEM_MAX_PUSH 512 153 struct drm_nouveau_gem_pushbuf_push { 154 uint32_t bo_index; 155 uint32_t pad; 156 uint64_t offset; 157 uint64_t length; 158 }; 159 160 struct drm_nouveau_gem_pushbuf { 161 uint32_t channel; 162 uint32_t nr_buffers; 163 uint64_t buffers; 164 uint32_t nr_relocs; 165 uint32_t nr_push; 166 uint64_t relocs; 167 uint64_t push; 168 uint32_t suffix0; 169 uint32_t suffix1; 170 uint64_t vram_available; 171 uint64_t gart_available; 172 }; 173 174 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 175 #define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002 176 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 177 struct drm_nouveau_gem_cpu_prep { 178 uint32_t handle; 179 uint32_t flags; 180 }; 181 182 struct drm_nouveau_gem_cpu_fini { 183 uint32_t handle; 184 }; 185 186 enum nouveau_bus_type { 187 NV_AGP = 0, 188 NV_PCI = 1, 189 NV_PCIE = 2, 190 }; 191 192 struct drm_nouveau_sarea { 193 }; 194 195 #define DRM_NOUVEAU_GETPARAM 0x00 196 #define DRM_NOUVEAU_SETPARAM 0x01 197 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 198 #define DRM_NOUVEAU_CHANNEL_FREE 0x03 199 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 200 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 201 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 202 #define DRM_NOUVEAU_GEM_NEW 0x40 203 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 204 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 205 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 206 #define DRM_NOUVEAU_GEM_INFO 0x44 207 208 /* The ioctls below are marked as staging */ 209 #define DRM_NOUVEAU_GEM_SET_TILING 0x50 210 #define DRM_NOUVEAU_GEM_PUSHBUF_2 0x51 211 212 #endif /* __NOUVEAU_DRM_H__ */ 213
