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      1 ============================
      2 User Guide for R600 Back-end
      3 ============================
      4 
      5 Introduction
      6 ============
      7 
      8 The R600 back-end provides ISA code generation for AMD GPUs, starting with
      9 the R600 family up until the current Volcanic Islands (GCN Gen 3).
     10 
     11 
     12 Assembler
     13 =========
     14 
     15 The assembler is currently considered experimental.
     16 
     17 For syntax examples look in test/MC/R600.
     18 
     19 Below some of the currently supported features (modulo bugs).  These
     20 all apply to the Southern Islands ISA, Sea Islands and Volcanic Islands
     21 are also supported but may be missing some instructions and have more bugs:
     22 
     23 DS Instructions
     24 ---------------
     25 All DS instructions are supported.
     26 
     27 MUBUF Instructions
     28 ------------------
     29 All non-atomic MUBUF instructions are supported.
     30 
     31 SMRD Instructions
     32 -----------------
     33 Only the s_load_dword* SMRD instructions are supported.
     34 
     35 SOP1 Instructions
     36 -----------------
     37 All SOP1 instructions are supported.
     38 
     39 SOP2 Instructions
     40 -----------------
     41 All SOP2 instructions are supported.
     42 
     43 SOPC Instructions
     44 -----------------
     45 All SOPC instructions are supported.
     46 
     47 SOPP Instructions
     48 -----------------
     49 
     50 Unless otherwise mentioned, all SOPP instructions that have one or more
     51 operands accept integer operands only.  No verification is performed
     52 on the operands, so it is up to the programmer to be familiar with the
     53 range or acceptable values.
     54 
     55 s_waitcnt
     56 ^^^^^^^^^
     57 
     58 s_waitcnt accepts named arguments to specify which memory counter(s) to
     59 wait for.
     60 
     61 .. code-block:: nasm
     62 
     63    // Wait for all counters to be 0
     64    s_waitcnt 0
     65 
     66    // Equivalent to s_waitcnt 0.  Counter names can also be delimited by
     67    // '&' or ','.
     68    s_waitcnt vmcnt(0) expcnt(0) lgkcmt(0)
     69 
     70    // Wait for vmcnt counter to be 1.
     71    s_waitcnt vmcnt(1)
     72 
     73 VOP1, VOP2, VOP3, VOPC Instructions
     74 -----------------------------------
     75 
     76 All 32-bit and 64-bit encodings should work.
     77 
     78 The assembler will automatically detect which encoding size to use for
     79 VOP1, VOP2, and VOPC instructions based on the operands.  If you want to force
     80 a specific encoding size, you can add an _e32 (for 32-bit encoding) or
     81 _e64 (for 64-bit encoding) suffix to the instruction.  Most, but not all
     82 instructions support an explicit suffix.  These are all valid assembly
     83 strings:
     84 
     85 .. code-block:: nasm
     86 
     87    v_mul_i32_i24 v1, v2, v3
     88    v_mul_i32_i24_e32 v1, v2, v3
     89    v_mul_i32_i24_e64 v1, v2, v3
     90