1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Hexagon Instruction Flags + 12 // 13 // *** Must match HexagonBaseInfo.h *** 14 //===----------------------------------------------------------------------===// 15 16 class IType<bits<5> t> { 17 bits<5> Value = t; 18 } 19 def TypePSEUDO : IType<0>; 20 def TypeALU32 : IType<1>; 21 def TypeCR : IType<2>; 22 def TypeJR : IType<3>; 23 def TypeJ : IType<4>; 24 def TypeLD : IType<5>; 25 def TypeST : IType<6>; 26 def TypeSYSTEM : IType<7>; 27 def TypeXTYPE : IType<8>; 28 def TypeENDLOOP: IType<31>; 29 30 // Maintain list of valid subtargets for each instruction. 31 class SubTarget<bits<6> value> { 32 bits<6> Value = value; 33 } 34 35 def HasAnySubT : SubTarget<0x3f>; // 111111 36 def HasV5SubT : SubTarget<0x3e>; // 111110 37 38 // Addressing modes for load/store instructions 39 class AddrModeType<bits<3> value> { 40 bits<3> Value = value; 41 } 42 43 def NoAddrMode : AddrModeType<0>; // No addressing mode 44 def Absolute : AddrModeType<1>; // Absolute addressing mode 45 def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode 46 def BaseImmOffset : AddrModeType<3>; // Indirect with offset 47 def BaseLongOffset : AddrModeType<4>; // Indirect with long offset 48 def BaseRegOffset : AddrModeType<5>; // Indirect with register offset 49 def PostInc : AddrModeType<6>; // Post increment addressing mode 50 51 class MemAccessSize<bits<4> value> { 52 bits<4> Value = value; 53 } 54 55 def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction. 56 def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb). 57 def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh). 58 def WordAccess : MemAccessSize<3>;// Word access instruction (memw). 59 def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd) 60 61 62 //===----------------------------------------------------------------------===// 63 // Instruction Class Declaration + 64 //===----------------------------------------------------------------------===// 65 66 class OpcodeHexagon { 67 field bits<32> Inst = ?; // Default to an invalid insn. 68 bits<4> IClass = 0; // ICLASS 69 bits<2> IParse = 0; // Parse bits. 70 71 let Inst{31-28} = IClass; 72 let Inst{15-14} = IParse; 73 74 bits<1> zero = 0; 75 } 76 77 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, 78 string cstr, InstrItinClass itin, IType type> 79 : Instruction { 80 let Namespace = "Hexagon"; 81 82 dag OutOperandList = outs; 83 dag InOperandList = ins; 84 let AsmString = asmstr; 85 let Pattern = pattern; 86 let Constraints = cstr; 87 let Itinerary = itin; 88 let Size = 4; 89 90 // SoftFail is a field the disassembler can use to provide a way for 91 // instructions to not match without killing the whole decode process. It is 92 // mainly used for ARM, but Tablegen expects this field to exist or it fails 93 // to build the decode table. 94 field bits<32> SoftFail = 0; 95 96 // *** Must match MCTargetDesc/HexagonBaseInfo.h *** 97 98 // Instruction type according to the ISA. 99 IType Type = type; 100 let TSFlags{4-0} = Type.Value; 101 102 // Solo instructions, i.e., those that cannot be in a packet with others. 103 bits<1> isSolo = 0; 104 let TSFlags{5} = isSolo; 105 // Packed only with A or X-type instructions. 106 bits<1> isSoloAX = 0; 107 let TSFlags{6} = isSoloAX; 108 // Only A-type instruction in first slot or nothing. 109 bits<1> isSoloAin1 = 0; 110 let TSFlags{7} = isSoloAin1; 111 112 // Predicated instructions. 113 bits<1> isPredicated = 0; 114 let TSFlags{8} = isPredicated; 115 bits<1> isPredicatedFalse = 0; 116 let TSFlags{9} = isPredicatedFalse; 117 bits<1> isPredicatedNew = 0; 118 let TSFlags{10} = isPredicatedNew; 119 bits<1> isPredicateLate = 0; 120 let TSFlags{11} = isPredicateLate; // Late predicate producer insn. 121 122 // New-value insn helper fields. 123 bits<1> isNewValue = 0; 124 let TSFlags{12} = isNewValue; // New-value consumer insn. 125 bits<1> hasNewValue = 0; 126 let TSFlags{13} = hasNewValue; // New-value producer insn. 127 bits<3> opNewValue = 0; 128 let TSFlags{16-14} = opNewValue; // New-value produced operand. 129 bits<1> isNVStorable = 0; 130 let TSFlags{17} = isNVStorable; // Store that can become new-value store. 131 bits<1> isNVStore = 0; 132 let TSFlags{18} = isNVStore; // New-value store insn. 133 bits<1> isCVLoadable = 0; 134 let TSFlags{19} = isCVLoadable; // Load that can become cur-value load. 135 bits<1> isCVLoad = 0; 136 let TSFlags{20} = isCVLoad; // Cur-value load insn. 137 138 // Immediate extender helper fields. 139 bits<1> isExtendable = 0; 140 let TSFlags{21} = isExtendable; // Insn may be extended. 141 bits<1> isExtended = 0; 142 let TSFlags{22} = isExtended; // Insn must be extended. 143 bits<3> opExtendable = 0; 144 let TSFlags{25-23} = opExtendable; // Which operand may be extended. 145 bits<1> isExtentSigned = 0; 146 let TSFlags{26} = isExtentSigned; // Signed or unsigned range. 147 bits<5> opExtentBits = 0; 148 let TSFlags{31-27} = opExtentBits; //Number of bits of range before extending. 149 bits<2> opExtentAlign = 0; 150 let TSFlags{33-32} = opExtentAlign; // Alignment exponent before extending. 151 152 // If an instruction is valid on a subtarget, set the corresponding 153 // bit from validSubTargets. 154 // By default, instruction is valid on all subtargets. 155 SubTarget validSubTargets = HasAnySubT; 156 let TSFlags{39-34} = validSubTargets.Value; 157 158 // Addressing mode for load/store instructions. 159 AddrModeType addrMode = NoAddrMode; 160 let TSFlags{42-40} = addrMode.Value; 161 162 // Memory access size for mem access instructions (load/store) 163 MemAccessSize accessSize = NoMemAccess; 164 let TSFlags{46-43} = accessSize.Value; 165 166 bits<1> isTaken = 0; 167 let TSFlags {47} = isTaken; // Branch prediction. 168 169 bits<1> isFP = 0; 170 let TSFlags {48} = isFP; // Floating-point. 171 172 // Fields used for relation models. 173 string BaseOpcode = ""; 174 string CextOpcode = ""; 175 string PredSense = ""; 176 string PNewValue = ""; 177 string NValueST = ""; // Set to "true" for new-value stores. 178 string InputType = ""; // Input is "imm" or "reg" type. 179 string isMEMri = "false"; // Set to "true" for load/store with MEMri operand. 180 string isFloat = "false"; // Set to "true" for the floating-point load/store. 181 string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions 182 183 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"), 184 ""); 185 let PNewValue = !if(isPredicatedNew, "new", ""); 186 let NValueST = !if(isNVStore, "true", "false"); 187 188 // *** Must match MCTargetDesc/HexagonBaseInfo.h *** 189 } 190 191 //===----------------------------------------------------------------------===// 192 // Instruction Classes Definitions + 193 //===----------------------------------------------------------------------===// 194 195 // LD Instruction Class in V2/V3/V4. 196 // Definition of the instruction class NOT CHANGED. 197 let mayLoad = 1 in 198 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 199 string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01> 200 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon; 201 202 let mayLoad = 1 in 203 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], 204 string cstr = ""> 205 : LDInst<outs, ins, asmstr, pattern, cstr>; 206 207 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 208 string cstr = ""> 209 : LDInst<outs, ins, asmstr, pattern, cstr>; 210 211 // LD Instruction Class in V2/V3/V4. 212 // Definition of the instruction class NOT CHANGED. 213 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [], 214 string cstr = ""> 215 : LDInst<outs, ins, asmstr, pattern, cstr>; 216 217 let mayLoad = 1 in 218 class LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 219 string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0> 220 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon; 221 222 // ST Instruction Class in V2/V3 can take SLOT0 only. 223 // ST Instruction Class in V4 can take SLOT0 & SLOT1. 224 // Definition of the instruction class CHANGED from V2/V3 to V4. 225 let mayStore = 1 in 226 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 227 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01> 228 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon; 229 230 class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], 231 string cstr = ""> 232 : STInst<outs, ins, asmstr, pattern, cstr>; 233 234 let mayStore = 1 in 235 class ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 236 string cstr = "", InstrItinClass itin = ST_tc_ld_SLOT0> 237 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon; 238 239 // ST Instruction Class in V2/V3 can take SLOT0 only. 240 // ST Instruction Class in V4 can take SLOT0 & SLOT1. 241 // Definition of the instruction class CHANGED from V2/V3 to V4. 242 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [], 243 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01> 244 : STInst<outs, ins, asmstr, pattern, cstr, itin>; 245 246 // SYSTEM Instruction Class in V4 can take SLOT0 only 247 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1. 248 class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 249 string cstr = "", InstrItinClass itin = ST_tc_3stall_SLOT0> 250 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeSYSTEM>, 251 OpcodeHexagon; 252 253 // ALU32 Instruction Class in V2/V3/V4. 254 // Definition of the instruction class NOT CHANGED. 255 class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 256 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> 257 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32>, OpcodeHexagon; 258 259 // ALU64 Instruction Class in V2/V3. 260 // XTYPE Instruction Class in V4. 261 // Definition of the instruction class NOT CHANGED. 262 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4. 263 class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 264 string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23> 265 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>, 266 OpcodeHexagon; 267 268 class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], 269 string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23> 270 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>; 271 272 273 // M Instruction Class in V2/V3. 274 // XTYPE Instruction Class in V4. 275 // Definition of the instruction class NOT CHANGED. 276 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. 277 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 278 string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23> 279 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>, 280 OpcodeHexagon; 281 282 // M Instruction Class in V2/V3. 283 // XTYPE Instruction Class in V4. 284 // Definition of the instruction class NOT CHANGED. 285 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. 286 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], 287 string cstr = "", InstrItinClass itin = M_tc_2_SLOT23> 288 : MInst<outs, ins, asmstr, pattern, cstr, itin>; 289 290 // S Instruction Class in V2/V3. 291 // XTYPE Instruction Class in V4. 292 // Definition of the instruction class NOT CHANGED. 293 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. 294 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 295 string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23> 296 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>, 297 OpcodeHexagon; 298 299 // S Instruction Class in V2/V3. 300 // XTYPE Instruction Class in V4. 301 // Definition of the instruction class NOT CHANGED. 302 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. 303 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], 304 string cstr = "", InstrItinClass itin = S_3op_tc_1_SLOT23> 305 : SInst<outs, ins, asmstr, pattern, cstr, itin>; 306 307 // J Instruction Class in V2/V3/V4. 308 // Definition of the instruction class NOT CHANGED. 309 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 310 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT23> 311 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>, OpcodeHexagon; 312 313 // JR Instruction Class in V2/V3/V4. 314 // Definition of the instruction class NOT CHANGED. 315 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 316 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2> 317 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJR>, OpcodeHexagon; 318 319 // CR Instruction Class in V2/V3/V4. 320 // Definition of the instruction class NOT CHANGED. 321 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 322 string cstr = "", InstrItinClass itin = CR_tc_2early_SLOT3> 323 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCR>, OpcodeHexagon; 324 325 let isCodeGenOnly = 1, isPseudo = 1 in 326 class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [], 327 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT0123> 328 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>, 329 OpcodeHexagon; 330 331 let isCodeGenOnly = 1, isPseudo = 1 in 332 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [], 333 string cstr = ""> 334 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>, 335 OpcodeHexagon; 336 337 let isCodeGenOnly = 1, isPseudo = 1 in 338 class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [], 339 string cstr=""> 340 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>, 341 OpcodeHexagon; 342 343 //===----------------------------------------------------------------------===// 344 // Instruction Classes Definitions - 345 //===----------------------------------------------------------------------===// 346 347 348 // 349 // ALU32 patterns 350 //. 351 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [], 352 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> 353 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; 354 355 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern = [], 356 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> 357 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; 358 359 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [], 360 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> 361 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; 362 363 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern = [], 364 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> 365 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; 366 367 // 368 // ALU64 patterns. 369 // 370 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [], 371 string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23> 372 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>; 373 374 class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [], 375 string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23> 376 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>; 377 378 // Post increment ST Instruction. 379 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [], 380 string cstr = ""> 381 : STInst<outs, ins, asmstr, pattern, cstr>; 382 383 let mayStore = 1 in 384 class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [], 385 string cstr = ""> 386 : STInst<outs, ins, asmstr, pattern, cstr>; 387 388 // Post increment LD Instruction. 389 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [], 390 string cstr = ""> 391 : LDInst<outs, ins, asmstr, pattern, cstr>; 392 393 let mayLoad = 1 in 394 class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [], 395 string cstr = ""> 396 : LDInst<outs, ins, asmstr, pattern, cstr>; 397 398 //===----------------------------------------------------------------------===// 399 // V4 Instruction Format Definitions + 400 //===----------------------------------------------------------------------===// 401 402 include "HexagonInstrFormatsV4.td" 403 404 //===----------------------------------------------------------------------===// 405 // V4 Instruction Format Definitions + 406 //===----------------------------------------------------------------------===// 407