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      1 //=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 // There are four SLOTS (four parallel pipelines) in Hexagon V4 machine.
     11 // This file describes that machine information.
     12 
     13 //
     14 //    |===========|==================================================|
     15 //    | PIPELINE  |              Instruction Classes                 |
     16 //    |===========|==================================================|
     17 //    | SLOT0     |  LD       ST    ALU32     MEMOP     NV    SYSTEM |
     18 //    |-----------|--------------------------------------------------|
     19 //    | SLOT1     |  LD       ST    ALU32                            |
     20 //    |-----------|--------------------------------------------------|
     21 //    | SLOT2     |  XTYPE          ALU32     J         JR           |
     22 //    |-----------|--------------------------------------------------|
     23 //    | SLOT3     |  XTYPE          ALU32     J         CR           |
     24 //    |===========|==================================================|
     25 
     26 // Functional Units.
     27 def SLOT0       : FuncUnit;
     28 def SLOT1       : FuncUnit;
     29 def SLOT2       : FuncUnit;
     30 def SLOT3       : FuncUnit;
     31 // Endloop is a pseudo instruction that is encoded with 2 bits in a packet
     32 // rather than taking an execution slot. This special unit is needed
     33 // to schedule an ENDLOOP with 4 other instructions.
     34 def SLOT_ENDLOOP: FuncUnit;
     35 
     36 // Itinerary classes.
     37 def PSEUDO      : InstrItinClass;
     38 def PSEUDOM   : InstrItinClass;
     39 // ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4.
     40 def DUPLEX      : InstrItinClass;
     41 def PREFIX      : InstrItinClass;
     42 def COMPOUND    : InstrItinClass;
     43 
     44 def ALU32_2op_tc_1_SLOT0123  : InstrItinClass;
     45 def ALU32_2op_tc_2early_SLOT0123  : InstrItinClass;
     46 def ALU32_3op_tc_2early_SLOT0123  : InstrItinClass;
     47 def ALU32_3op_tc_1_SLOT0123  : InstrItinClass;
     48 def ALU32_3op_tc_2_SLOT0123  : InstrItinClass;
     49 def ALU32_ADDI_tc_1_SLOT0123 : InstrItinClass;
     50 def ALU64_tc_1_SLOT23        : InstrItinClass;
     51 def ALU64_tc_1or2_SLOT23     : InstrItinClass;
     52 def ALU64_tc_2_SLOT23        : InstrItinClass;
     53 def ALU64_tc_2early_SLOT23   : InstrItinClass;
     54 def ALU64_tc_3x_SLOT23       : InstrItinClass;
     55 def CR_tc_2_SLOT3            : InstrItinClass;
     56 def CR_tc_2early_SLOT23      : InstrItinClass;
     57 def CR_tc_2early_SLOT3       : InstrItinClass;
     58 def CR_tc_3x_SLOT23          : InstrItinClass;
     59 def CR_tc_3x_SLOT3           : InstrItinClass;
     60 def J_tc_2early_SLOT23       : InstrItinClass;
     61 def J_tc_2early_SLOT2        : InstrItinClass;
     62 def LD_tc_ld_SLOT01          : InstrItinClass;
     63 def LD_tc_ld_SLOT0           : InstrItinClass;
     64 def LD_tc_3or4stall_SLOT0    : InstrItinClass;
     65 def M_tc_1_SLOT23            : InstrItinClass;
     66 def M_tc_1or2_SLOT23         : InstrItinClass;
     67 def M_tc_2_SLOT23            : InstrItinClass;
     68 def M_tc_3_SLOT23            : InstrItinClass;
     69 def M_tc_3x_SLOT23           : InstrItinClass;
     70 def M_tc_3or4x_SLOT23        : InstrItinClass;
     71 def ST_tc_st_SLOT01          : InstrItinClass;
     72 def ST_tc_st_SLOT0           : InstrItinClass;
     73 def ST_tc_ld_SLOT0           : InstrItinClass;
     74 def ST_tc_3stall_SLOT0       : InstrItinClass;
     75 def S_2op_tc_1_SLOT23        : InstrItinClass;
     76 def S_2op_tc_2_SLOT23        : InstrItinClass;
     77 def S_2op_tc_2early_SLOT23   : InstrItinClass;
     78 def S_2op_tc_3or4x_SLOT23    : InstrItinClass;
     79 def S_3op_tc_1_SLOT23        : InstrItinClass;
     80 def S_3op_tc_1or2_SLOT23     : InstrItinClass;
     81 def S_3op_tc_2_SLOT23        : InstrItinClass;
     82 def S_3op_tc_2early_SLOT23   : InstrItinClass;
     83 def S_3op_tc_3_SLOT23        : InstrItinClass;
     84 def S_3op_tc_3x_SLOT23       : InstrItinClass;
     85 def NCJ_tc_3or4stall_SLOT0   : InstrItinClass;
     86 def V2LDST_tc_ld_SLOT01      : InstrItinClass;
     87 def V2LDST_tc_st_SLOT0       : InstrItinClass;
     88 def V2LDST_tc_st_SLOT01      : InstrItinClass;
     89 def V4LDST_tc_ld_SLOT01      : InstrItinClass;
     90 def V4LDST_tc_st_SLOT0       : InstrItinClass;
     91 def V4LDST_tc_st_SLOT01      : InstrItinClass;
     92 def J_tc_2early_SLOT0123     : InstrItinClass;
     93 def EXTENDER_tc_1_SLOT0123   : InstrItinClass;
     94 
     95 
     96 def HexagonItinerariesV4 :
     97       ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
     98         // ALU32
     99         InstrItinData<ALU32_2op_tc_1_SLOT0123  ,
    100                      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
    101         InstrItinData<ALU32_2op_tc_2early_SLOT0123,
    102                      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
    103         InstrItinData<ALU32_3op_tc_1_SLOT0123   ,
    104                      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
    105         InstrItinData<ALU32_3op_tc_2early_SLOT0123,
    106                      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
    107         InstrItinData<ALU32_3op_tc_2_SLOT0123   ,
    108                      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
    109         InstrItinData<ALU32_ADDI_tc_1_SLOT0123  ,
    110                      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
    111 
    112         // ALU64
    113         InstrItinData<ALU64_tc_1_SLOT23      , [InstrStage<1, [SLOT2, SLOT3]>]>,
    114         InstrItinData<ALU64_tc_1or2_SLOT23   , [InstrStage<1, [SLOT2, SLOT3]>]>,
    115         InstrItinData<ALU64_tc_2_SLOT23      , [InstrStage<1, [SLOT2, SLOT3]>]>,
    116         InstrItinData<ALU64_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
    117         InstrItinData<ALU64_tc_3x_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>]>,
    118 
    119         // CR -> System
    120         InstrItinData<CR_tc_2_SLOT3          , [InstrStage<1, [SLOT3]>]>,
    121         InstrItinData<CR_tc_2early_SLOT3     , [InstrStage<1, [SLOT3]>]>,
    122         InstrItinData<CR_tc_3x_SLOT3         , [InstrStage<1, [SLOT3]>]>,
    123 
    124         // Jump (conditional/unconditional/return etc)
    125         // CR
    126         InstrItinData<CR_tc_2early_SLOT23    , [InstrStage<1, [SLOT2, SLOT3]>]>,
    127         InstrItinData<CR_tc_3x_SLOT23        , [InstrStage<1, [SLOT2, SLOT3]>]>,
    128         // J
    129         InstrItinData<J_tc_2early_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>]>,
    130         // JR
    131         InstrItinData<J_tc_2early_SLOT2      , [InstrStage<1, [SLOT2]>]>,
    132 
    133         //Load
    134         InstrItinData<LD_tc_ld_SLOT01        , [InstrStage<1, [SLOT0, SLOT1]>]>,
    135         InstrItinData<LD_tc_ld_SLOT0         , [InstrStage<1, [SLOT0]>]>,
    136         InstrItinData<LD_tc_3or4stall_SLOT0  , [InstrStage<1, [SLOT0]>]>,
    137 
    138         // M
    139         InstrItinData<M_tc_1_SLOT23          , [InstrStage<1, [SLOT2, SLOT3]>]>,
    140         InstrItinData<M_tc_1or2_SLOT23       , [InstrStage<1, [SLOT2, SLOT3]>]>,
    141         InstrItinData<M_tc_2_SLOT23          , [InstrStage<1, [SLOT2, SLOT3]>]>,
    142         InstrItinData<M_tc_3_SLOT23          , [InstrStage<1, [SLOT2, SLOT3]>]>,
    143         InstrItinData<M_tc_3x_SLOT23         , [InstrStage<1, [SLOT2, SLOT3]>]>,
    144         InstrItinData<M_tc_3or4x_SLOT23      , [InstrStage<1, [SLOT2, SLOT3]>]>,
    145 
    146         // Store
    147         // ST
    148         InstrItinData<ST_tc_st_SLOT01        , [InstrStage<1, [SLOT0, SLOT1]>]>,
    149         // ST0
    150         InstrItinData<ST_tc_st_SLOT0         , [InstrStage<1, [SLOT0]>]>,
    151         InstrItinData<ST_tc_ld_SLOT0         , [InstrStage<1, [SLOT0]>]>,
    152 
    153         // S
    154         InstrItinData<S_2op_tc_1_SLOT23      , [InstrStage<1, [SLOT2, SLOT3]>]>,
    155         InstrItinData<S_2op_tc_2_SLOT23      , [InstrStage<1, [SLOT2, SLOT3]>]>,
    156         InstrItinData<S_2op_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
    157         InstrItinData<S_2op_tc_3or4x_SLOT23  , [InstrStage<1, [SLOT2, SLOT3]>]>,
    158         InstrItinData<S_3op_tc_1_SLOT23      , [InstrStage<1, [SLOT2, SLOT3]>]>,
    159         InstrItinData<S_3op_tc_1or2_SLOT23   , [InstrStage<1, [SLOT2, SLOT3]>]>,
    160         InstrItinData<S_3op_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
    161         InstrItinData<S_3op_tc_2_SLOT23      , [InstrStage<1, [SLOT2, SLOT3]>]>,
    162         InstrItinData<S_3op_tc_3_SLOT23      , [InstrStage<1, [SLOT2, SLOT3]>]>,
    163         InstrItinData<S_3op_tc_3x_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>]>,
    164 
    165         // SYS
    166         InstrItinData<ST_tc_3stall_SLOT0     , [InstrStage<1, [SLOT0]>]>,
    167 
    168         // New Value Compare Jump
    169         InstrItinData<NCJ_tc_3or4stall_SLOT0 , [InstrStage<1, [SLOT0]>]>,
    170 
    171         // Mem ops - MEM_V4
    172         InstrItinData<V2LDST_tc_st_SLOT0     , [InstrStage<1, [SLOT0]>]>,
    173         InstrItinData<V2LDST_tc_ld_SLOT01    , [InstrStage<1, [SLOT0, SLOT1]>]>,
    174         InstrItinData<V2LDST_tc_st_SLOT01    , [InstrStage<1, [SLOT0, SLOT1]>]>,
    175         InstrItinData<V4LDST_tc_st_SLOT0     , [InstrStage<1, [SLOT0]>]>,
    176         InstrItinData<V4LDST_tc_ld_SLOT01    , [InstrStage<1, [SLOT0, SLOT1]>]>,
    177         InstrItinData<V4LDST_tc_st_SLOT01    , [InstrStage<1, [SLOT0, SLOT1]>]>,
    178 
    179         InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>]>,
    180 
    181         // ENDLOOP
    182         InstrItinData<J_tc_2early_SLOT0123   , [InstrStage<1, [SLOT_ENDLOOP]>]>,
    183 
    184         // Extender/PREFIX
    185         InstrItinData<EXTENDER_tc_1_SLOT0123,
    186                      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
    187 
    188         InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>]>,
    189         InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
    190         InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
    191                                 InstrStage<1, [SLOT2, SLOT3]>]>
    192       ]>;
    193 
    194 def HexagonModelV4 : SchedMachineModel {
    195   // Max issue per cycle == bundle width.
    196   let IssueWidth = 4;
    197   let Itineraries = HexagonItinerariesV4;
    198   let LoadLatency = 1;
    199 }
    200 
    201 //===----------------------------------------------------------------------===//
    202 // Hexagon V4 Resource Definitions -
    203 //===----------------------------------------------------------------------===//
    204