1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides Hexagon specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "HexagonMCTargetDesc.h" 15 #include "HexagonMCAsmInfo.h" 16 #include "MCTargetDesc/HexagonInstPrinter.h" 17 #include "llvm/MC/MCCodeGenInfo.h" 18 #include "llvm/MC/MCELFStreamer.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCRegisterInfo.h" 21 #include "llvm/MC/MCStreamer.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/MC/MachineLocation.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 27 using namespace llvm; 28 29 #define GET_INSTRINFO_MC_DESC 30 #include "HexagonGenInstrInfo.inc" 31 32 #define GET_SUBTARGETINFO_MC_DESC 33 #include "HexagonGenSubtargetInfo.inc" 34 35 #define GET_REGINFO_MC_DESC 36 #include "HexagonGenRegisterInfo.inc" 37 38 MCInstrInfo *llvm::createHexagonMCInstrInfo() { 39 MCInstrInfo *X = new MCInstrInfo(); 40 InitHexagonMCInstrInfo(X); 41 return X; 42 } 43 44 static MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT) { 45 MCRegisterInfo *X = new MCRegisterInfo(); 46 InitHexagonMCRegisterInfo(X, Hexagon::R0); 47 return X; 48 } 49 50 static MCSubtargetInfo * 51 createHexagonMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { 52 MCSubtargetInfo *X = new MCSubtargetInfo(); 53 InitHexagonMCSubtargetInfo(X, TT, CPU, FS); 54 return X; 55 } 56 57 static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, 58 StringRef TT) { 59 MCAsmInfo *MAI = new HexagonMCAsmInfo(TT); 60 61 // VirtualFP = (R30 + #0). 62 MCCFIInstruction Inst = 63 MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0); 64 MAI->addInitialFrameState(Inst); 65 66 return MAI; 67 } 68 69 static MCCodeGenInfo *createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM, 70 CodeModel::Model CM, 71 CodeGenOpt::Level OL) { 72 MCCodeGenInfo *X = new MCCodeGenInfo(); 73 // For the time being, use static relocations, since there's really no 74 // support for PIC yet. 75 X->InitMCCodeGenInfo(Reloc::Static, CM, OL); 76 return X; 77 } 78 79 static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T, 80 unsigned SyntaxVariant, 81 const MCAsmInfo &MAI, 82 const MCInstrInfo &MII, 83 const MCRegisterInfo &MRI) { 84 if (SyntaxVariant == 0) 85 return(new HexagonInstPrinter(MAI, MII, MRI)); 86 else 87 return nullptr; 88 } 89 90 // Force static initialization. 91 extern "C" void LLVMInitializeHexagonTargetMC() { 92 // Register the MC asm info. 93 RegisterMCAsmInfoFn X(TheHexagonTarget, createHexagonMCAsmInfo); 94 95 // Register the MC codegen info. 96 TargetRegistry::RegisterMCCodeGenInfo(TheHexagonTarget, 97 createHexagonMCCodeGenInfo); 98 99 // Register the MC instruction info. 100 TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget, 101 createHexagonMCInstrInfo); 102 103 // Register the MC register info. 104 TargetRegistry::RegisterMCRegInfo(TheHexagonTarget, 105 createHexagonMCRegisterInfo); 106 107 // Register the MC subtarget info. 108 TargetRegistry::RegisterMCSubtargetInfo(TheHexagonTarget, 109 createHexagonMCSubtargetInfo); 110 111 // Register the MC Code Emitter 112 TargetRegistry::RegisterMCCodeEmitter(TheHexagonTarget, 113 createHexagonMCCodeEmitter); 114 115 // Register the MC Inst Printer 116 TargetRegistry::RegisterMCInstPrinter(TheHexagonTarget, 117 createHexagonMCInstPrinter); 118 119 // Register the asm backend 120 TargetRegistry::RegisterMCAsmBackend(TheHexagonTarget, 121 createHexagonAsmBackend); 122 } 123