1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the MipsAsmBackend class. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #include "MCTargetDesc/MipsFixupKinds.h" 16 #include "MCTargetDesc/MipsAsmBackend.h" 17 #include "MCTargetDesc/MipsMCTargetDesc.h" 18 #include "llvm/MC/MCAsmBackend.h" 19 #include "llvm/MC/MCAssembler.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCDirectives.h" 22 #include "llvm/MC/MCELFObjectWriter.h" 23 #include "llvm/MC/MCFixupKindInfo.h" 24 #include "llvm/MC/MCObjectWriter.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/MathExtras.h" 28 #include "llvm/Support/raw_ostream.h" 29 30 using namespace llvm; 31 32 // Prepare value for the target space for it 33 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 34 MCContext *Ctx = nullptr) { 35 36 unsigned Kind = Fixup.getKind(); 37 38 // Add/subtract and shift 39 switch (Kind) { 40 default: 41 return 0; 42 case FK_Data_2: 43 case FK_GPRel_4: 44 case FK_Data_4: 45 case FK_Data_8: 46 case Mips::fixup_Mips_LO16: 47 case Mips::fixup_Mips_GPREL16: 48 case Mips::fixup_Mips_GPOFF_HI: 49 case Mips::fixup_Mips_GPOFF_LO: 50 case Mips::fixup_Mips_GOT_PAGE: 51 case Mips::fixup_Mips_GOT_OFST: 52 case Mips::fixup_Mips_GOT_DISP: 53 case Mips::fixup_Mips_GOT_LO16: 54 case Mips::fixup_Mips_CALL_LO16: 55 case Mips::fixup_MICROMIPS_LO16: 56 case Mips::fixup_MICROMIPS_GOT_PAGE: 57 case Mips::fixup_MICROMIPS_GOT_OFST: 58 case Mips::fixup_MICROMIPS_GOT_DISP: 59 case Mips::fixup_MIPS_PCLO16: 60 break; 61 case Mips::fixup_Mips_PC16: 62 // So far we are only using this type for branches. 63 // For branches we start 1 instruction after the branch 64 // so the displacement will be one instruction size less. 65 Value -= 4; 66 // The displacement is then divided by 4 to give us an 18 bit 67 // address range. Forcing a signed division because Value can be negative. 68 Value = (int64_t)Value / 4; 69 // We now check if Value can be encoded as a 16-bit signed immediate. 70 if (!isIntN(16, Value) && Ctx) 71 Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup"); 72 break; 73 case Mips::fixup_MIPS_PC19_S2: 74 // Forcing a signed division because Value can be negative. 75 Value = (int64_t)Value / 4; 76 // We now check if Value can be encoded as a 19-bit signed immediate. 77 if (!isIntN(19, Value) && Ctx) 78 Ctx->FatalError(Fixup.getLoc(), "out of range PC19 fixup"); 79 break; 80 case Mips::fixup_Mips_26: 81 // So far we are only using this type for jumps. 82 // The displacement is then divided by 4 to give us an 28 bit 83 // address range. 84 Value >>= 2; 85 break; 86 case Mips::fixup_Mips_HI16: 87 case Mips::fixup_Mips_GOT_Local: 88 case Mips::fixup_Mips_GOT_HI16: 89 case Mips::fixup_Mips_CALL_HI16: 90 case Mips::fixup_MICROMIPS_HI16: 91 case Mips::fixup_MIPS_PCHI16: 92 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1. 93 Value = ((Value + 0x8000) >> 16) & 0xffff; 94 break; 95 case Mips::fixup_Mips_HIGHER: 96 // Get the 3rd 16-bits. 97 Value = ((Value + 0x80008000LL) >> 32) & 0xffff; 98 break; 99 case Mips::fixup_Mips_HIGHEST: 100 // Get the 4th 16-bits. 101 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; 102 break; 103 case Mips::fixup_MICROMIPS_26_S1: 104 Value >>= 1; 105 break; 106 case Mips::fixup_MICROMIPS_PC7_S1: 107 Value -= 4; 108 // Forcing a signed division because Value can be negative. 109 Value = (int64_t) Value / 2; 110 // We now check if Value can be encoded as a 7-bit signed immediate. 111 if (!isIntN(7, Value) && Ctx) 112 Ctx->FatalError(Fixup.getLoc(), "out of range PC7 fixup"); 113 break; 114 case Mips::fixup_MICROMIPS_PC10_S1: 115 Value -= 2; 116 // Forcing a signed division because Value can be negative. 117 Value = (int64_t) Value / 2; 118 // We now check if Value can be encoded as a 10-bit signed immediate. 119 if (!isIntN(10, Value) && Ctx) 120 Ctx->FatalError(Fixup.getLoc(), "out of range PC10 fixup"); 121 break; 122 case Mips::fixup_MICROMIPS_PC16_S1: 123 Value -= 4; 124 // Forcing a signed division because Value can be negative. 125 Value = (int64_t)Value / 2; 126 // We now check if Value can be encoded as a 16-bit signed immediate. 127 if (!isIntN(16, Value) && Ctx) 128 Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup"); 129 break; 130 case Mips::fixup_MIPS_PC18_S3: 131 // Forcing a signed division because Value can be negative. 132 Value = (int64_t)Value / 8; 133 // We now check if Value can be encoded as a 18-bit signed immediate. 134 if (!isIntN(18, Value) && Ctx) 135 Ctx->FatalError(Fixup.getLoc(), "out of range PC18 fixup"); 136 break; 137 case Mips::fixup_MIPS_PC21_S2: 138 Value -= 4; 139 // Forcing a signed division because Value can be negative. 140 Value = (int64_t) Value / 4; 141 // We now check if Value can be encoded as a 21-bit signed immediate. 142 if (!isIntN(21, Value) && Ctx) 143 Ctx->FatalError(Fixup.getLoc(), "out of range PC21 fixup"); 144 break; 145 case Mips::fixup_MIPS_PC26_S2: 146 Value -= 4; 147 // Forcing a signed division because Value can be negative. 148 Value = (int64_t) Value / 4; 149 // We now check if Value can be encoded as a 26-bit signed immediate. 150 if (!isIntN(26, Value) && Ctx) 151 Ctx->FatalError(Fixup.getLoc(), "out of range PC26 fixup"); 152 break; 153 } 154 155 return Value; 156 } 157 158 MCObjectWriter * 159 MipsAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const { 160 return createMipsELFObjectWriter(OS, 161 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); 162 } 163 164 // Little-endian fixup data byte ordering: 165 // mips32r2: a | b | x | x 166 // microMIPS: x | x | a | b 167 168 static bool needsMMLEByteOrder(unsigned Kind) { 169 return Kind != Mips::fixup_MICROMIPS_PC10_S1 && 170 Kind >= Mips::fixup_MICROMIPS_26_S1 && 171 Kind < Mips::LastTargetFixupKind; 172 } 173 174 // Calculate index for microMIPS specific little endian byte order 175 static unsigned calculateMMLEIndex(unsigned i) { 176 assert(i <= 3 && "Index out of range!"); 177 178 return (1 - i / 2) * 2 + i % 2; 179 } 180 181 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided 182 /// data fragment, at the offset specified by the fixup and following the 183 /// fixup kind as appropriate. 184 void MipsAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 185 unsigned DataSize, uint64_t Value, 186 bool IsPCRel) const { 187 MCFixupKind Kind = Fixup.getKind(); 188 Value = adjustFixupValue(Fixup, Value); 189 190 if (!Value) 191 return; // Doesn't change encoding. 192 193 // Where do we start in the object 194 unsigned Offset = Fixup.getOffset(); 195 // Number of bytes we need to fixup 196 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; 197 // Used to point to big endian bytes 198 unsigned FullSize; 199 200 switch ((unsigned)Kind) { 201 case FK_Data_2: 202 case Mips::fixup_Mips_16: 203 case Mips::fixup_MICROMIPS_PC10_S1: 204 FullSize = 2; 205 break; 206 case FK_Data_8: 207 case Mips::fixup_Mips_64: 208 FullSize = 8; 209 break; 210 case FK_Data_4: 211 default: 212 FullSize = 4; 213 break; 214 } 215 216 // Grab current value, if any, from bits. 217 uint64_t CurVal = 0; 218 219 bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind); 220 221 for (unsigned i = 0; i != NumBytes; ++i) { 222 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) 223 : i) 224 : (FullSize - 1 - i); 225 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); 226 } 227 228 uint64_t Mask = ((uint64_t)(-1) >> 229 (64 - getFixupKindInfo(Kind).TargetSize)); 230 CurVal |= Value & Mask; 231 232 // Write out the fixed up bytes back to the code/data bits. 233 for (unsigned i = 0; i != NumBytes; ++i) { 234 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) 235 : i) 236 : (FullSize - 1 - i); 237 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); 238 } 239 } 240 241 const MCFixupKindInfo &MipsAsmBackend:: 242 getFixupKindInfo(MCFixupKind Kind) const { 243 const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = { 244 // This table *must* be in same the order of fixup_* kinds in 245 // MipsFixupKinds.h. 246 // 247 // name offset bits flags 248 { "fixup_Mips_16", 0, 16, 0 }, 249 { "fixup_Mips_32", 0, 32, 0 }, 250 { "fixup_Mips_REL32", 0, 32, 0 }, 251 { "fixup_Mips_26", 0, 26, 0 }, 252 { "fixup_Mips_HI16", 0, 16, 0 }, 253 { "fixup_Mips_LO16", 0, 16, 0 }, 254 { "fixup_Mips_GPREL16", 0, 16, 0 }, 255 { "fixup_Mips_LITERAL", 0, 16, 0 }, 256 { "fixup_Mips_GOT_Global", 0, 16, 0 }, 257 { "fixup_Mips_GOT_Local", 0, 16, 0 }, 258 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 259 { "fixup_Mips_CALL16", 0, 16, 0 }, 260 { "fixup_Mips_GPREL32", 0, 32, 0 }, 261 { "fixup_Mips_SHIFT5", 6, 5, 0 }, 262 { "fixup_Mips_SHIFT6", 6, 5, 0 }, 263 { "fixup_Mips_64", 0, 64, 0 }, 264 { "fixup_Mips_TLSGD", 0, 16, 0 }, 265 { "fixup_Mips_GOTTPREL", 0, 16, 0 }, 266 { "fixup_Mips_TPREL_HI", 0, 16, 0 }, 267 { "fixup_Mips_TPREL_LO", 0, 16, 0 }, 268 { "fixup_Mips_TLSLDM", 0, 16, 0 }, 269 { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, 270 { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, 271 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 272 { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, 273 { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, 274 { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, 275 { "fixup_Mips_GOT_OFST", 0, 16, 0 }, 276 { "fixup_Mips_GOT_DISP", 0, 16, 0 }, 277 { "fixup_Mips_HIGHER", 0, 16, 0 }, 278 { "fixup_Mips_HIGHEST", 0, 16, 0 }, 279 { "fixup_Mips_GOT_HI16", 0, 16, 0 }, 280 { "fixup_Mips_GOT_LO16", 0, 16, 0 }, 281 { "fixup_Mips_CALL_HI16", 0, 16, 0 }, 282 { "fixup_Mips_CALL_LO16", 0, 16, 0 }, 283 { "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, 284 { "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, 285 { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, 286 { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, 287 { "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 288 { "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 289 { "fixup_MICROMIPS_26_S1", 0, 26, 0 }, 290 { "fixup_MICROMIPS_HI16", 0, 16, 0 }, 291 { "fixup_MICROMIPS_LO16", 0, 16, 0 }, 292 { "fixup_MICROMIPS_GOT16", 0, 16, 0 }, 293 { "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel }, 294 { "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, 295 { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 296 { "fixup_MICROMIPS_CALL16", 0, 16, 0 }, 297 { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, 298 { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 }, 299 { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 }, 300 { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 }, 301 { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 }, 302 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 }, 303 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 }, 304 { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, 305 { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 } 306 }; 307 308 const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = { 309 // This table *must* be in same the order of fixup_* kinds in 310 // MipsFixupKinds.h. 311 // 312 // name offset bits flags 313 { "fixup_Mips_16", 16, 16, 0 }, 314 { "fixup_Mips_32", 0, 32, 0 }, 315 { "fixup_Mips_REL32", 0, 32, 0 }, 316 { "fixup_Mips_26", 6, 26, 0 }, 317 { "fixup_Mips_HI16", 16, 16, 0 }, 318 { "fixup_Mips_LO16", 16, 16, 0 }, 319 { "fixup_Mips_GPREL16", 16, 16, 0 }, 320 { "fixup_Mips_LITERAL", 16, 16, 0 }, 321 { "fixup_Mips_GOT_Global", 16, 16, 0 }, 322 { "fixup_Mips_GOT_Local", 16, 16, 0 }, 323 { "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 324 { "fixup_Mips_CALL16", 16, 16, 0 }, 325 { "fixup_Mips_GPREL32", 0, 32, 0 }, 326 { "fixup_Mips_SHIFT5", 21, 5, 0 }, 327 { "fixup_Mips_SHIFT6", 21, 5, 0 }, 328 { "fixup_Mips_64", 0, 64, 0 }, 329 { "fixup_Mips_TLSGD", 16, 16, 0 }, 330 { "fixup_Mips_GOTTPREL", 16, 16, 0 }, 331 { "fixup_Mips_TPREL_HI", 16, 16, 0 }, 332 { "fixup_Mips_TPREL_LO", 16, 16, 0 }, 333 { "fixup_Mips_TLSLDM", 16, 16, 0 }, 334 { "fixup_Mips_DTPREL_HI", 16, 16, 0 }, 335 { "fixup_Mips_DTPREL_LO", 16, 16, 0 }, 336 { "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel }, 337 { "fixup_Mips_GPOFF_HI", 16, 16, 0 }, 338 { "fixup_Mips_GPOFF_LO", 16, 16, 0 }, 339 { "fixup_Mips_GOT_PAGE", 16, 16, 0 }, 340 { "fixup_Mips_GOT_OFST", 16, 16, 0 }, 341 { "fixup_Mips_GOT_DISP", 16, 16, 0 }, 342 { "fixup_Mips_HIGHER", 16, 16, 0 }, 343 { "fixup_Mips_HIGHEST", 16, 16, 0 }, 344 { "fixup_Mips_GOT_HI16", 16, 16, 0 }, 345 { "fixup_Mips_GOT_LO16", 16, 16, 0 }, 346 { "fixup_Mips_CALL_HI16", 16, 16, 0 }, 347 { "fixup_Mips_CALL_LO16", 16, 16, 0 }, 348 { "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel }, 349 { "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel }, 350 { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel }, 351 { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, 352 { "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 353 { "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 354 { "fixup_MICROMIPS_26_S1", 6, 26, 0 }, 355 { "fixup_MICROMIPS_HI16", 16, 16, 0 }, 356 { "fixup_MICROMIPS_LO16", 16, 16, 0 }, 357 { "fixup_MICROMIPS_GOT16", 16, 16, 0 }, 358 { "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel }, 359 { "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel }, 360 { "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel }, 361 { "fixup_MICROMIPS_CALL16", 16, 16, 0 }, 362 { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 }, 363 { "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 }, 364 { "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 }, 365 { "fixup_MICROMIPS_TLS_GD", 16, 16, 0 }, 366 { "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 }, 367 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 }, 368 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 }, 369 { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 }, 370 { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 } 371 }; 372 373 if (Kind < FirstTargetFixupKind) 374 return MCAsmBackend::getFixupKindInfo(Kind); 375 376 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 377 "Invalid kind!"); 378 379 if (IsLittle) 380 return LittleEndianInfos[Kind - FirstTargetFixupKind]; 381 return BigEndianInfos[Kind - FirstTargetFixupKind]; 382 } 383 384 /// WriteNopData - Write an (optimal) nop sequence of Count bytes 385 /// to the given output. If the target cannot generate such a sequence, 386 /// it should return an error. 387 /// 388 /// \return - True on success. 389 bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 390 // Check for a less than instruction size number of bytes 391 // FIXME: 16 bit instructions are not handled yet here. 392 // We shouldn't be using a hard coded number for instruction size. 393 394 // If the count is not 4-byte aligned, we must be writing data into the text 395 // section (otherwise we have unaligned instructions, and thus have far 396 // bigger problems), so just write zeros instead. 397 for (uint64_t i = 0, e = Count % 4; i != e; ++i) 398 OW->Write8(0); 399 400 uint64_t NumNops = Count / 4; 401 for (uint64_t i = 0; i != NumNops; ++i) 402 OW->Write32(0); 403 return true; 404 } 405 406 /// processFixupValue - Target hook to process the literal value of a fixup 407 /// if necessary. 408 void MipsAsmBackend::processFixupValue(const MCAssembler &Asm, 409 const MCAsmLayout &Layout, 410 const MCFixup &Fixup, 411 const MCFragment *DF, 412 const MCValue &Target, 413 uint64_t &Value, 414 bool &IsResolved) { 415 // At this point we'll ignore the value returned by adjustFixupValue as 416 // we are only checking if the fixup can be applied correctly. We have 417 // access to MCContext from here which allows us to report a fatal error 418 // with *possibly* a source code location. 419 (void)adjustFixupValue(Fixup, Value, &Asm.getContext()); 420 } 421 422 // MCAsmBackend 423 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, 424 const MCRegisterInfo &MRI, 425 StringRef TT, 426 StringRef CPU) { 427 return new MipsAsmBackend(T, Triple(TT).getOS(), 428 /*IsLittle*/true, /*Is64Bit*/false); 429 } 430 431 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, 432 const MCRegisterInfo &MRI, 433 StringRef TT, 434 StringRef CPU) { 435 return new MipsAsmBackend(T, Triple(TT).getOS(), 436 /*IsLittle*/false, /*Is64Bit*/false); 437 } 438 439 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, 440 const MCRegisterInfo &MRI, 441 StringRef TT, 442 StringRef CPU) { 443 return new MipsAsmBackend(T, Triple(TT).getOS(), 444 /*IsLittle*/true, /*Is64Bit*/true); 445 } 446 447 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, 448 const MCRegisterInfo &MRI, 449 StringRef TT, 450 StringRef CPU) { 451 return new MipsAsmBackend(T, Triple(TT).getOS(), 452 /*IsLittle*/false, /*Is64Bit*/true); 453 } 454
