1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes Mips32r6 instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 include "Mips32r6InstrFormats.td" 15 16 // Notes about removals/changes from MIPS32r6: 17 // Reencoded: jr -> jalr 18 // Reencoded: jr.hb -> jalr.hb 19 20 def brtarget21 : Operand<OtherVT> { 21 let EncoderMethod = "getBranchTarget21OpValue"; 22 let OperandType = "OPERAND_PCREL"; 23 let DecoderMethod = "DecodeBranchTarget21"; 24 let ParserMatchClass = MipsJumpTargetAsmOperand; 25 } 26 27 def brtarget26 : Operand<OtherVT> { 28 let EncoderMethod = "getBranchTarget26OpValue"; 29 let OperandType = "OPERAND_PCREL"; 30 let DecoderMethod = "DecodeBranchTarget26"; 31 let ParserMatchClass = MipsJumpTargetAsmOperand; 32 } 33 34 def jmpoffset16 : Operand<OtherVT> { 35 let EncoderMethod = "getJumpOffset16OpValue"; 36 let ParserMatchClass = MipsJumpTargetAsmOperand; 37 } 38 39 def calloffset16 : Operand<iPTR> { 40 let EncoderMethod = "getJumpOffset16OpValue"; 41 let ParserMatchClass = MipsJumpTargetAsmOperand; 42 } 43 44 //===----------------------------------------------------------------------===// 45 // 46 // Instruction Encodings 47 // 48 //===----------------------------------------------------------------------===// 49 50 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>; 51 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>; 52 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>; 53 class AUI_ENC : AUI_FM; 54 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>; 55 56 class BAL_ENC : BAL_FM; 57 class BALC_ENC : BRANCH_OFF26_FM<0b111010>; 58 class BC_ENC : BRANCH_OFF26_FM<0b110010>; 59 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>, 60 DecodeDisambiguates<"AddiGroupBranch">; 61 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>, 62 DecodeDisambiguatedBy<"DaddiGroupBranch">; 63 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>, 64 DecodeDisambiguates<"DaddiGroupBranch">; 65 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>, 66 DecodeDisambiguatedBy<"DaddiGroupBranch">; 67 68 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>, 69 DecodeDisambiguates<"BgtzlGroupBranch">; 70 class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>, 71 DecodeDisambiguatedBy<"BlezlGroupBranch">; 72 class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>, 73 DecodeDisambiguatedBy<"BlezGroupBranch">; 74 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>, 75 DecodeDisambiguates<"BlezlGroupBranch">; 76 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>, 77 DecodeDisambiguatedBy<"BgtzGroupBranch">; 78 79 class BLTC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZL>, 80 DecodeDisambiguatedBy<"BgtzlGroupBranch">; 81 class BLTUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZ>, 82 DecodeDisambiguatedBy<"BgtzGroupBranch">; 83 84 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>, 85 DecodeDisambiguatedBy<"BlezlGroupBranch">; 86 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>, 87 DecodeDisambiguates<"BgtzGroupBranch">; 88 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>, 89 DecodeDisambiguatedBy<"BgtzlGroupBranch">; 90 91 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>; 92 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>, 93 DecodeDisambiguates<"BlezGroupBranch">; 94 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>; 95 96 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>; 97 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>; 98 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>; 99 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>; 100 101 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>; 102 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>; 103 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>; 104 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>; 105 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>, 106 DecodeDisambiguatedBy<"BlezGroupBranch">; 107 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>, 108 DecodeDisambiguatedBy<"DaddiGroupBranch">; 109 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>, 110 DecodeDisambiguatedBy<"AddiGroupBranch">; 111 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>; 112 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>; 113 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>; 114 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>; 115 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>; 116 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>; 117 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>; 118 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>; 119 120 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>; 121 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>; 122 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>; 123 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>; 124 125 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>; 126 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>; 127 128 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>; 129 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>; 130 131 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>; 132 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>; 133 134 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>; 135 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>; 136 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>; 137 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>; 138 139 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>; 140 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>; 141 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>; 142 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>; 143 144 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>; 145 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>; 146 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>; 147 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>; 148 149 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>; 150 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>; 151 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>; 152 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>; 153 154 class CACHE_ENC : SPECIAL3_MEM_FM<OPCODE6_CACHE>; 155 class PREF_ENC : SPECIAL3_MEM_FM<OPCODE6_PREF>; 156 157 class LDC2_R6_ENC : COP2LDST_FM<OPCODE5_LDC2>; 158 class LWC2_R6_ENC : COP2LDST_FM<OPCODE5_LWC2>; 159 class SDC2_R6_ENC : COP2LDST_FM<OPCODE5_SDC2>; 160 class SWC2_R6_ENC : COP2LDST_FM<OPCODE5_SWC2>; 161 162 class LSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_LSA>; 163 164 class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>; 165 class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>; 166 167 class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>; 168 class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>; 169 170 class SDBBP_R6_ENC : SPECIAL_SDBBP_FM; 171 172 //===----------------------------------------------------------------------===// 173 // 174 // Instruction Multiclasses 175 // 176 //===----------------------------------------------------------------------===// 177 178 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, 179 RegisterOperand FGROpnd, 180 SDPatternOperator Op = null_frag> { 181 dag OutOperandList = (outs FGRCCOpnd:$fd); 182 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); 183 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft"); 184 list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))]; 185 } 186 187 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr, 188 RegisterOperand FGROpnd>{ 189 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>, 190 CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, 191 ISA_MIPS32R6; 192 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>, 193 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>, 194 ISA_MIPS32R6; 195 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>, 196 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>, 197 ISA_MIPS32R6; 198 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>, 199 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>, 200 ISA_MIPS32R6; 201 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>, 202 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>, 203 ISA_MIPS32R6; 204 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>, 205 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>, 206 ISA_MIPS32R6; 207 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>, 208 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>, 209 ISA_MIPS32R6; 210 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>, 211 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>, 212 ISA_MIPS32R6; 213 def CMP_SAF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SAF>, 214 CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, 215 ISA_MIPS32R6; 216 def CMP_SUN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUN>, 217 CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, 218 ISA_MIPS32R6; 219 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>, 220 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, 221 ISA_MIPS32R6; 222 def CMP_SUEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUEQ>, 223 CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, 224 ISA_MIPS32R6; 225 def CMP_SLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLT>, 226 CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, 227 ISA_MIPS32R6; 228 def CMP_SULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULT>, 229 CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, 230 ISA_MIPS32R6; 231 def CMP_SLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLE>, 232 CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, 233 ISA_MIPS32R6; 234 def CMP_SULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULE>, 235 CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, 236 ISA_MIPS32R6; 237 } 238 239 //===----------------------------------------------------------------------===// 240 // 241 // Instruction Descriptions 242 // 243 //===----------------------------------------------------------------------===// 244 245 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 246 Operand ImmOpnd> { 247 dag OutOperandList = (outs GPROpnd:$rs); 248 dag InOperandList = (ins ImmOpnd:$imm); 249 string AsmString = !strconcat(instr_asm, "\t$rs, $imm"); 250 list<dag> Pattern = []; 251 } 252 253 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>; 254 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>; 255 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>; 256 257 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 258 Operand ImmOpnd> { 259 dag OutOperandList = (outs GPROpnd:$rd); 260 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp); 261 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp"); 262 list<dag> Pattern = []; 263 } 264 265 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>; 266 267 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 268 dag OutOperandList = (outs GPROpnd:$rs); 269 dag InOperandList = (ins simm16:$imm); 270 string AsmString = !strconcat(instr_asm, "\t$rs, $imm"); 271 list<dag> Pattern = []; 272 } 273 274 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>; 275 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>; 276 277 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 278 dag OutOperandList = (outs GPROpnd:$rs); 279 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm); 280 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm"); 281 list<dag> Pattern = []; 282 } 283 284 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>; 285 286 class BRANCH_DESC_BASE { 287 bit isBranch = 1; 288 bit isTerminator = 1; 289 bit hasDelaySlot = 0; 290 } 291 292 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE { 293 dag InOperandList = (ins opnd:$offset); 294 dag OutOperandList = (outs); 295 string AsmString = !strconcat(instr_asm, "\t$offset"); 296 bit isBarrier = 1; 297 } 298 299 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd, 300 RegisterOperand GPROpnd> : BRANCH_DESC_BASE { 301 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset); 302 dag OutOperandList = (outs); 303 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset"); 304 list<Register> Defs = [AT]; 305 } 306 307 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd, 308 RegisterOperand GPROpnd> : BRANCH_DESC_BASE { 309 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset); 310 dag OutOperandList = (outs); 311 string AsmString = !strconcat(instr_asm, "\t$rs, $offset"); 312 list<Register> Defs = [AT]; 313 } 314 315 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd, 316 RegisterOperand GPROpnd> : BRANCH_DESC_BASE { 317 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); 318 dag OutOperandList = (outs); 319 string AsmString = !strconcat(instr_asm, "\t$rt, $offset"); 320 list<Register> Defs = [AT]; 321 } 322 323 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> { 324 bit isCall = 1; 325 bit hasDelaySlot = 1; 326 list<Register> Defs = [RA]; 327 } 328 329 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> { 330 bit isCall = 1; 331 list<Register> Defs = [RA]; 332 } 333 334 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>; 335 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>; 336 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>; 337 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>; 338 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>; 339 340 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>; 341 class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>; 342 343 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>; 344 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>; 345 346 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>; 347 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>; 348 349 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>; 350 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>; 351 352 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE { 353 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset); 354 dag OutOperandList = (outs); 355 string AsmString = instr_asm; 356 bit hasDelaySlot = 1; 357 } 358 359 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">; 360 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">; 361 362 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE { 363 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset); 364 dag OutOperandList = (outs); 365 string AsmString = instr_asm; 366 bit hasDelaySlot = 1; 367 } 368 369 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">; 370 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">; 371 372 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>; 373 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>; 374 375 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd, 376 RegisterOperand GPROpnd> { 377 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); 378 string AsmString = !strconcat(opstr, "\t$rt, $offset"); 379 list<dag> Pattern = []; 380 bit isTerminator = 1; 381 bit hasDelaySlot = 0; 382 } 383 384 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16, 385 GPR32Opnd> { 386 bit isCall = 1; 387 list<Register> Defs = [RA]; 388 } 389 390 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> { 391 bit isBarrier = 1; 392 list<Register> Defs = [AT]; 393 } 394 395 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> { 396 bit isBranch = 1; 397 bit isIndirectBranch = 1; 398 bit hasDelaySlot = 1; 399 bit isTerminator=1; 400 bit isBarrier=1; 401 } 402 403 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 404 dag OutOperandList = (outs GPROpnd:$rd); 405 dag InOperandList = (ins GPROpnd:$rt); 406 string AsmString = !strconcat(instr_asm, "\t$rd, $rt"); 407 list<dag> Pattern = []; 408 } 409 410 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>; 411 412 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 413 SDPatternOperator Op=null_frag> { 414 dag OutOperandList = (outs GPROpnd:$rd); 415 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 416 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 417 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))]; 418 419 // This instruction doesn't trap division by zero itself. We must insert 420 // teq instructions as well. 421 bit usesCustomInserter = 1; 422 } 423 424 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>; 425 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>; 426 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>; 427 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>; 428 429 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> { 430 list<Register> Defs = [RA]; 431 } 432 433 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> { 434 list<Register> Defs = [RA]; 435 } 436 437 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> { 438 list<Register> Defs = [RA]; 439 } 440 441 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> { 442 list<Register> Defs = [RA]; 443 } 444 445 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> { 446 list<Register> Defs = [RA]; 447 } 448 449 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> { 450 list<Register> Defs = [RA]; 451 } 452 453 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 454 SDPatternOperator Op=null_frag> { 455 dag OutOperandList = (outs GPROpnd:$rd); 456 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 457 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 458 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))]; 459 } 460 461 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>; 462 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>; 463 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>; 464 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>; 465 466 class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 467 dag OutOperandList = (outs FGROpnd:$fd); 468 dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft); 469 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 470 list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in, 471 FGROpnd:$ft, 472 FGROpnd:$fs))]; 473 string Constraints = "$fd_in = $fd"; 474 } 475 476 class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> { 477 // We must insert a SUBREG_TO_REG around $fd_in 478 bit usesCustomInserter = 1; 479 } 480 class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>; 481 482 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 483 dag OutOperandList = (outs GPROpnd:$rd); 484 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 485 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 486 list<dag> Pattern = []; 487 } 488 489 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>; 490 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>; 491 492 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 493 dag OutOperandList = (outs FGROpnd:$fd); 494 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft); 495 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 496 list<dag> Pattern = []; 497 string Constraints = "$fd_in = $fd"; 498 } 499 500 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>; 501 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>; 502 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>; 503 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>; 504 505 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 506 dag OutOperandList = (outs FGROpnd:$fd); 507 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); 508 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 509 list<dag> Pattern = []; 510 } 511 512 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>; 513 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>; 514 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>; 515 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>; 516 517 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>; 518 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>; 519 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>; 520 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>; 521 522 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 523 dag OutOperandList = (outs FGROpnd:$fd); 524 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); 525 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 526 list<dag> Pattern = []; 527 } 528 529 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>; 530 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>; 531 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>; 532 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>; 533 534 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 535 dag OutOperandList = (outs FGROpnd:$fd); 536 dag InOperandList = (ins FGROpnd:$fs); 537 string AsmString = !strconcat(instr_asm, "\t$fd, $fs"); 538 list<dag> Pattern = []; 539 } 540 541 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>; 542 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>; 543 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>; 544 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>; 545 546 class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd, 547 RegisterOperand GPROpnd> { 548 dag OutOperandList = (outs); 549 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); 550 string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); 551 list<dag> Pattern = []; 552 string DecoderMethod = "DecodeCacheOpR6"; 553 } 554 555 class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>; 556 class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd>; 557 558 class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> { 559 dag OutOperandList = (outs COPOpnd:$rt); 560 dag InOperandList = (ins mem_simm11:$addr); 561 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 562 list<dag> Pattern = []; 563 bit mayLoad = 1; 564 string DecoderMethod = "DecodeFMemCop2R6"; 565 } 566 567 class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>; 568 class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd>; 569 570 class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> { 571 dag OutOperandList = (outs); 572 dag InOperandList = (ins COPOpnd:$rt, mem_simm11:$addr); 573 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 574 list<dag> Pattern = []; 575 bit mayStore = 1; 576 string DecoderMethod = "DecodeFMemCop2R6"; 577 } 578 579 class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd>; 580 class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd>; 581 582 class LSA_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 583 Operand ImmOpnd> { 584 dag OutOperandList = (outs GPROpnd:$rd); 585 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2); 586 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2"); 587 list<dag> Pattern = []; 588 } 589 590 class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2>; 591 592 class LL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 593 dag OutOperandList = (outs GPROpnd:$rt); 594 dag InOperandList = (ins mem_simm9:$addr); 595 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 596 list<dag> Pattern = []; 597 bit mayLoad = 1; 598 } 599 600 class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd>; 601 602 class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 603 dag OutOperandList = (outs GPROpnd:$dst); 604 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); 605 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 606 list<dag> Pattern = []; 607 bit mayStore = 1; 608 string Constraints = "$rt = $dst"; 609 } 610 611 class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd>; 612 613 class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 614 dag OutOperandList = (outs GPROpnd:$rd); 615 dag InOperandList = (ins GPROpnd:$rs); 616 string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); 617 } 618 619 class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> : 620 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> { 621 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))]; 622 } 623 624 class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> : 625 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> { 626 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))]; 627 } 628 629 class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd>; 630 class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd>; 631 632 class SDBBP_R6_DESC { 633 dag OutOperandList = (outs); 634 dag InOperandList = (ins uimm20:$code_); 635 string AsmString = "sdbbp\t$code_"; 636 list<dag> Pattern = []; 637 } 638 639 //===----------------------------------------------------------------------===// 640 // 641 // Instruction Definitions 642 // 643 //===----------------------------------------------------------------------===// 644 645 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6; 646 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6; 647 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6; 648 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6; 649 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6; 650 def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6; 651 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6; 652 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6; 653 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6; 654 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6; 655 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6; 656 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6; 657 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6; 658 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6; 659 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6; 660 def BGEC : BGEC_ENC, BGEC_DESC, ISA_MIPS32R6; 661 def BGEUC : BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6; 662 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6; 663 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6; 664 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6; 665 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6; 666 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6; 667 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6; 668 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6; 669 def BLTC : BLTC_ENC, BLTC_DESC, ISA_MIPS32R6; 670 def BLTUC : BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6; 671 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6; 672 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6; 673 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6; 674 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6; 675 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6; 676 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6; 677 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6; 678 def CACHE_R6 : CACHE_ENC, CACHE_DESC, ISA_MIPS32R6; 679 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6; 680 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6; 681 def CLO_R6 : CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6; 682 def CLZ_R6 : CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6; 683 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>; 684 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>; 685 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6; 686 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6; 687 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6; 688 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6; 689 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6; 690 def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6; 691 def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6; 692 def LSA_R6 : LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6; 693 def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6; 694 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6; 695 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6; 696 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6; 697 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6; 698 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6; 699 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6; 700 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6; 701 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6; 702 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6; 703 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6; 704 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6; 705 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6; 706 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6; 707 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6; 708 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6; 709 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6; 710 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6; 711 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; 712 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6; 713 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6; 714 def NAL; // BAL with rd=0 715 def PREF_R6 : PREF_ENC, PREF_DESC, ISA_MIPS32R6; 716 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6; 717 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6; 718 def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6; 719 def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6; 720 def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; 721 def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; 722 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6; 723 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6; 724 def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32; 725 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6; 726 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6; 727 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6; 728 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6; 729 def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6; 730 731 //===----------------------------------------------------------------------===// 732 // 733 // Instruction Aliases 734 // 735 //===----------------------------------------------------------------------===// 736 737 def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6; 738 def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6; 739 740 //===----------------------------------------------------------------------===// 741 // 742 // Patterns and Pseudo Instructions 743 // 744 //===----------------------------------------------------------------------===// 745 746 // f32 comparisons supported via another comparison 747 def : MipsPat<(setone f32:$lhs, f32:$rhs), 748 (NOR (CMP_UEQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6; 749 def : MipsPat<(seto f32:$lhs, f32:$rhs), 750 (NOR (CMP_UN_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6; 751 def : MipsPat<(setune f32:$lhs, f32:$rhs), 752 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6; 753 def : MipsPat<(seteq f32:$lhs, f32:$rhs), (CMP_EQ_S f32:$lhs, f32:$rhs)>, 754 ISA_MIPS32R6; 755 def : MipsPat<(setgt f32:$lhs, f32:$rhs), (CMP_LE_S f32:$rhs, f32:$lhs)>, 756 ISA_MIPS32R6; 757 def : MipsPat<(setge f32:$lhs, f32:$rhs), (CMP_LT_S f32:$rhs, f32:$lhs)>, 758 ISA_MIPS32R6; 759 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_LT_S f32:$lhs, f32:$rhs)>, 760 ISA_MIPS32R6; 761 def : MipsPat<(setle f32:$lhs, f32:$rhs), (CMP_LE_S f32:$lhs, f32:$rhs)>, 762 ISA_MIPS32R6; 763 def : MipsPat<(setne f32:$lhs, f32:$rhs), 764 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6; 765 766 // f64 comparisons supported via another comparison 767 def : MipsPat<(setone f64:$lhs, f64:$rhs), 768 (NOR (CMP_UEQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6; 769 def : MipsPat<(seto f64:$lhs, f64:$rhs), 770 (NOR (CMP_UN_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6; 771 def : MipsPat<(setune f64:$lhs, f64:$rhs), 772 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6; 773 def : MipsPat<(seteq f64:$lhs, f64:$rhs), (CMP_EQ_D f64:$lhs, f64:$rhs)>, 774 ISA_MIPS32R6; 775 def : MipsPat<(setgt f64:$lhs, f64:$rhs), (CMP_LE_D f64:$rhs, f64:$lhs)>, 776 ISA_MIPS32R6; 777 def : MipsPat<(setge f64:$lhs, f64:$rhs), (CMP_LT_D f64:$rhs, f64:$lhs)>, 778 ISA_MIPS32R6; 779 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_LT_D f64:$lhs, f64:$rhs)>, 780 ISA_MIPS32R6; 781 def : MipsPat<(setle f64:$lhs, f64:$rhs), (CMP_LE_D f64:$lhs, f64:$rhs)>, 782 ISA_MIPS32R6; 783 def : MipsPat<(setne f64:$lhs, f64:$rhs), 784 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6; 785 786 // i32 selects 787 def : MipsPat<(select i32:$cond, i32:$t, i32:$f), 788 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>, 789 ISA_MIPS32R6; 790 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, i32:$f), 791 (OR (SELEQZ i32:$t, i32:$cond), (SELNEZ i32:$f, i32:$cond))>, 792 ISA_MIPS32R6; 793 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, i32:$f), 794 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>, 795 ISA_MIPS32R6; 796 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i32:$t, i32:$f), 797 (OR (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)), 798 (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>, 799 ISA_MIPS32R6; 800 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f), 801 (OR (SELNEZ i32:$t, (XORi i32:$cond, immZExt16:$imm)), 802 (SELEQZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>, 803 ISA_MIPS32R6; 804 def : MipsPat<(select (i32 (setgt i32:$cond, immSExt16Plus1:$imm)), i32:$t, 805 i32:$f), 806 (OR (SELEQZ i32:$t, (SLTi i32:$cond, (Plus1 imm:$imm))), 807 (SELNEZ i32:$f, (SLTi i32:$cond, (Plus1 imm:$imm))))>, 808 ISA_MIPS32R6; 809 def : MipsPat<(select (i32 (setugt i32:$cond, immSExt16Plus1:$imm)), 810 i32:$t, i32:$f), 811 (OR (SELEQZ i32:$t, (SLTiu i32:$cond, (Plus1 imm:$imm))), 812 (SELNEZ i32:$f, (SLTiu i32:$cond, (Plus1 imm:$imm))))>, 813 ISA_MIPS32R6; 814 815 def : MipsPat<(select i32:$cond, i32:$t, immz), 816 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6; 817 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, immz), 818 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6; 819 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, immz), 820 (SELEQZ i32:$t, i32:$cond)>, ISA_MIPS32R6; 821 def : MipsPat<(select i32:$cond, immz, i32:$f), 822 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6; 823 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i32:$f), 824 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6; 825 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i32:$f), 826 (SELNEZ i32:$f, i32:$cond)>, ISA_MIPS32R6; 827
