1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the X86 conditional move and set on condition 11 // instructions. 12 // 13 //===----------------------------------------------------------------------===// 14 15 16 // SetCC instructions. 17 multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> { 18 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", 19 isCommutable = 1, SchedRW = [WriteALU] in { 20 def NAME#16rr 21 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 22 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"), 23 [(set GR16:$dst, 24 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))], 25 IIC_CMOV16_RR>, TB, OpSize16; 26 def NAME#32rr 27 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 28 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"), 29 [(set GR32:$dst, 30 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))], 31 IIC_CMOV32_RR>, TB, OpSize32; 32 def NAME#64rr 33 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 34 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"), 35 [(set GR64:$dst, 36 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))], 37 IIC_CMOV32_RR>, TB; 38 } 39 40 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", 41 SchedRW = [WriteALULd, ReadAfterLd] in { 42 def NAME#16rm 43 : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), 44 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"), 45 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), 46 CondNode, EFLAGS))], IIC_CMOV16_RM>, 47 TB, OpSize16; 48 def NAME#32rm 49 : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), 50 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"), 51 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), 52 CondNode, EFLAGS))], IIC_CMOV32_RM>, 53 TB, OpSize32; 54 def NAME#64rm 55 :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), 56 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"), 57 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), 58 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB; 59 } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst" 60 } // end multiclass 61 62 63 // Conditional Moves. 64 defm CMOVO : CMOV<0x40, "cmovo" , X86_COND_O>; 65 defm CMOVNO : CMOV<0x41, "cmovno", X86_COND_NO>; 66 defm CMOVB : CMOV<0x42, "cmovb" , X86_COND_B>; 67 defm CMOVAE : CMOV<0x43, "cmovae", X86_COND_AE>; 68 defm CMOVE : CMOV<0x44, "cmove" , X86_COND_E>; 69 defm CMOVNE : CMOV<0x45, "cmovne", X86_COND_NE>; 70 defm CMOVBE : CMOV<0x46, "cmovbe", X86_COND_BE>; 71 defm CMOVA : CMOV<0x47, "cmova" , X86_COND_A>; 72 defm CMOVS : CMOV<0x48, "cmovs" , X86_COND_S>; 73 defm CMOVNS : CMOV<0x49, "cmovns", X86_COND_NS>; 74 defm CMOVP : CMOV<0x4A, "cmovp" , X86_COND_P>; 75 defm CMOVNP : CMOV<0x4B, "cmovnp", X86_COND_NP>; 76 defm CMOVL : CMOV<0x4C, "cmovl" , X86_COND_L>; 77 defm CMOVGE : CMOV<0x4D, "cmovge", X86_COND_GE>; 78 defm CMOVLE : CMOV<0x4E, "cmovle", X86_COND_LE>; 79 defm CMOVG : CMOV<0x4F, "cmovg" , X86_COND_G>; 80 81 82 // SetCC instructions. 83 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> { 84 let Uses = [EFLAGS] in { 85 def r : I<opc, MRMXr, (outs GR8:$dst), (ins), 86 !strconcat(Mnemonic, "\t$dst"), 87 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))], 88 IIC_SET_R>, TB, Sched<[WriteALU]>; 89 def m : I<opc, MRMXm, (outs), (ins i8mem:$dst), 90 !strconcat(Mnemonic, "\t$dst"), 91 [(store (X86setcc OpNode, EFLAGS), addr:$dst)], 92 IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>; 93 } // Uses = [EFLAGS] 94 } 95 96 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set 97 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set 98 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than 99 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal 100 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to 101 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to 102 defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>; // unsigned less than or equal 103 defm SETA : SETCC<0x97, "seta", X86_COND_A>; // unsigned greater than 104 defm SETS : SETCC<0x98, "sets", X86_COND_S>; // is signed bit set 105 defm SETNS : SETCC<0x99, "setns", X86_COND_NS>; // is not signed 106 defm SETP : SETCC<0x9A, "setp", X86_COND_P>; // is parity bit set 107 defm SETNP : SETCC<0x9B, "setnp", X86_COND_NP>; // is parity bit not set 108 defm SETL : SETCC<0x9C, "setl", X86_COND_L>; // signed less than 109 defm SETGE : SETCC<0x9D, "setge", X86_COND_GE>; // signed greater or equal 110 defm SETLE : SETCC<0x9E, "setle", X86_COND_LE>; // signed less than or equal 111 defm SETG : SETCC<0x9F, "setg", X86_COND_G>; // signed greater than 112 113
