1 ; RUN: llc < %s -mtriple=aarch64-eabi -O=3 | FileCheck %s 2 3 define void @test() { 4 ; CHECK: dmb sy 5 call void @llvm.aarch64.dmb(i32 15) 6 ; CHECK: dmb osh 7 call void @llvm.aarch64.dmb(i32 3) 8 ; CHECK: dsb sy 9 call void @llvm.aarch64.dsb(i32 15) 10 ; CHECK: dsb ishld 11 call void @llvm.aarch64.dsb(i32 9) 12 ; CHECK: isb 13 call void @llvm.aarch64.isb(i32 15) 14 ret void 15 } 16 17 ; Important point is that the compiler should not reorder memory access 18 ; instructions around DMB. 19 ; Failure to do so, two STRs will collapse into one STP. 20 define void @test_dmb_reordering(i32 %a, i32 %b, i32* %d) { 21 store i32 %a, i32* %d ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}] 22 23 call void @llvm.aarch64.dmb(i32 15); CHECK: dmb sy 24 25 %d1 = getelementptr i32, i32* %d, i64 1 26 store i32 %b, i32* %d1 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #4] 27 28 ret void 29 } 30 31 ; Similarly for DSB. 32 define void @test_dsb_reordering(i32 %a, i32 %b, i32* %d) { 33 store i32 %a, i32* %d ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}] 34 35 call void @llvm.aarch64.dsb(i32 15); CHECK: dsb sy 36 37 %d1 = getelementptr i32, i32* %d, i64 1 38 store i32 %b, i32* %d1 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #4] 39 40 ret void 41 } 42 43 ; And ISB. 44 define void @test_isb_reordering(i32 %a, i32 %b, i32* %d) { 45 store i32 %a, i32* %d ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}] 46 47 call void @llvm.aarch64.isb(i32 15); CHECK: isb 48 49 %d1 = getelementptr i32, i32* %d, i64 1 50 store i32 %b, i32* %d1 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #4] 51 52 ret void 53 } 54 55 declare void @llvm.aarch64.dmb(i32) 56 declare void @llvm.aarch64.dsb(i32) 57 declare void @llvm.aarch64.isb(i32) 58
