1 ; RUN: llc -march=hexagon -disable-hexagon-misched < %s | FileCheck %s 2 ; Check that we generate dual stores in one packet in V4 3 4 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}= 5 ; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}= 6 7 define i32 @main(i32 %v, i32* %p1, i32* %p2) nounwind { 8 entry: 9 store i32 %v, i32* %p1, align 4 10 store i32 %v, i32* %p2, align 4 11 ret i32 0 12 } 13
