1 ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s 2 ; Check that we generate a hardware loop instruction. 3 ; CHECK: endloop0 4 5 @A = common global [400 x i8] zeroinitializer, align 8 6 @B = common global [400 x i8] zeroinitializer, align 8 7 @C = common global [400 x i8] zeroinitializer, align 8 8 9 define void @run() nounwind { 10 entry: 11 br label %polly.loop_body 12 13 polly.loop_after: ; preds = %polly.loop_body 14 ret void 15 16 polly.loop_body: ; preds = %entry, %polly.loop_body 17 %polly.loopiv16 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ] 18 %polly.next_loopiv = add i32 %polly.loopiv16, 4 19 %p_vector_iv14 = or i32 %polly.loopiv16, 1 20 %p_vector_iv3 = add i32 %p_vector_iv14, 1 21 %p_vector_iv415 = or i32 %polly.loopiv16, 3 22 %p_arrayidx = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %polly.loopiv16 23 %p_arrayidx5 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %p_vector_iv14 24 %p_arrayidx6 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %p_vector_iv3 25 %p_arrayidx7 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %p_vector_iv415 26 store i8 123, i8* %p_arrayidx, align 1 27 store i8 123, i8* %p_arrayidx5, align 1 28 store i8 123, i8* %p_arrayidx6, align 1 29 store i8 123, i8* %p_arrayidx7, align 1 30 %0 = icmp slt i32 %polly.next_loopiv, 400 31 br i1 %0, label %polly.loop_body, label %polly.loop_after 32 } 33
