1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s 2 ; Hexagon Programmer's Reference Manual 11.1.2 ALU32/PERM 3 4 ; Combine words into doubleword 5 declare i64 @llvm.hexagon.A4.combineri(i32, i32) 6 define i64 @A4_combineri(i32 %a) { 7 %z = call i64 @llvm.hexagon.A4.combineri(i32 %a, i32 0) 8 ret i64 %z 9 } 10 ; CHECK: = combine(r0, #0) 11 12 declare i64 @llvm.hexagon.A4.combineir(i32, i32) 13 define i64 @A4_combineir(i32 %a) { 14 %z = call i64 @llvm.hexagon.A4.combineir(i32 0, i32 %a) 15 ret i64 %z 16 } 17 ; CHECK: = combine(#0, r0) 18 19 declare i64 @llvm.hexagon.A2.combineii(i32, i32) 20 define i64 @A2_combineii() { 21 %z = call i64 @llvm.hexagon.A2.combineii(i32 0, i32 0) 22 ret i64 %z 23 } 24 ; CHECK: r1:0 = combine(#0, #0) 25 26 declare i32 @llvm.hexagon.A2.combine.hh(i32, i32) 27 define i32 @A2_combine_hh(i32 %a, i32 %b) { 28 %z = call i32 @llvm.hexagon.A2.combine.hh(i32 %a, i32 %b) 29 ret i32 %z 30 } 31 ; CHECK: r0 = combine(r0.h, r1.h) 32 33 declare i32 @llvm.hexagon.A2.combine.hl(i32, i32) 34 define i32 @A2_combine_hl(i32 %a, i32 %b) { 35 %z = call i32 @llvm.hexagon.A2.combine.hl(i32 %a, i32 %b) 36 ret i32 %z 37 } 38 ; CHECK: r0 = combine(r0.h, r1.l) 39 40 declare i32 @llvm.hexagon.A2.combine.lh(i32, i32) 41 define i32 @A2_combine_lh(i32 %a, i32 %b) { 42 %z = call i32 @llvm.hexagon.A2.combine.lh(i32 %a, i32 %b) 43 ret i32 %z 44 } 45 ; CHECK: r0 = combine(r0.l, r1.h) 46 47 declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) 48 define i32 @A2_combine_ll(i32 %a, i32 %b) { 49 %z = call i32 @llvm.hexagon.A2.combine.ll(i32 %a, i32 %b) 50 ret i32 %z 51 } 52 ; CHECK: r0 = combine(r0.l, r1.l) 53 54 declare i64 @llvm.hexagon.A2.combinew(i32, i32) 55 define i64 @A2_combinew(i32 %a, i32 %b) { 56 %z = call i64 @llvm.hexagon.A2.combinew(i32 %a, i32 %b) 57 ret i64 %z 58 } 59 ; CHECK: r1:0 = combine(r0, r1) 60 61 ; Mux 62 declare i32 @llvm.hexagon.C2.muxri(i32, i32, i32) 63 define i32 @C2_muxri(i32 %a, i32 %b) { 64 %z = call i32 @llvm.hexagon.C2.muxri(i32 %a, i32 0, i32 %b) 65 ret i32 %z 66 } 67 ; CHECK: r0 = mux(p0, #0, r1) 68 69 declare i32 @llvm.hexagon.C2.muxir(i32, i32, i32) 70 define i32 @C2_muxir(i32 %a, i32 %b) { 71 %z = call i32 @llvm.hexagon.C2.muxir(i32 %a, i32 %b, i32 0) 72 ret i32 %z 73 } 74 ; CHECK: r0 = mux(p0, r1, #0) 75 76 declare i32 @llvm.hexagon.C2.mux(i32, i32, i32) 77 define i32 @C2_mux(i32 %a, i32 %b, i32 %c) { 78 %z = call i32 @llvm.hexagon.C2.mux(i32 %a, i32 %b, i32 %c) 79 ret i32 %z 80 } 81 ; CHECK: r0 = mux(p0, r1, r2) 82 83 ; Shift word by 16 84 declare i32 @llvm.hexagon.A2.aslh(i32) 85 define i32 @A2_aslh(i32 %a) { 86 %z = call i32 @llvm.hexagon.A2.aslh(i32 %a) 87 ret i32 %z 88 } 89 ; CHECK: r0 = aslh(r0) 90 91 declare i32 @llvm.hexagon.A2.asrh(i32) 92 define i32 @A2_asrh(i32 %a) { 93 %z = call i32 @llvm.hexagon.A2.asrh(i32 %a) 94 ret i32 %z 95 } 96 ; CHECK: r0 = asrh(r0) 97 98 ; Pack high and low halfwords 99 declare i64 @llvm.hexagon.S2.packhl(i32, i32) 100 define i64 @S2_packhl(i32 %a, i32 %b) { 101 %z = call i64 @llvm.hexagon.S2.packhl(i32 %a, i32 %b) 102 ret i64 %z 103 } 104 ; CHECK: r1:0 = packhl(r0, r1) 105