1 ; Test the MSA fixed-point to floating point conversion intrinsics that are 2 ; encoded with the 2RF instruction format. 3 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 6 7 @llvm_mips_ffql_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 8 @llvm_mips_ffql_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 9 10 define void @llvm_mips_ffql_w_test() nounwind { 11 entry: 12 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ffql_w_ARG1 13 %1 = tail call <4 x float> @llvm.mips.ffql.w(<8 x i16> %0) 14 store <4 x float> %1, <4 x float>* @llvm_mips_ffql_w_RES 15 ret void 16 } 17 18 declare <4 x float> @llvm.mips.ffql.w(<8 x i16>) nounwind 19 20 ; CHECK: llvm_mips_ffql_w_test: 21 ; CHECK: ld.h 22 ; CHECK: ffql.w 23 ; CHECK: st.w 24 ; CHECK: .size llvm_mips_ffql_w_test 25 ; 26 @llvm_mips_ffql_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 27 @llvm_mips_ffql_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16 28 29 define void @llvm_mips_ffql_d_test() nounwind { 30 entry: 31 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ffql_d_ARG1 32 %1 = tail call <2 x double> @llvm.mips.ffql.d(<4 x i32> %0) 33 store <2 x double> %1, <2 x double>* @llvm_mips_ffql_d_RES 34 ret void 35 } 36 37 declare <2 x double> @llvm.mips.ffql.d(<4 x i32>) nounwind 38 39 ; CHECK: llvm_mips_ffql_d_test: 40 ; CHECK: ld.w 41 ; CHECK: ffql.d 42 ; CHECK: st.d 43 ; CHECK: .size llvm_mips_ffql_d_test 44 ; 45 @llvm_mips_ffqr_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 46 @llvm_mips_ffqr_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 47 48 define void @llvm_mips_ffqr_w_test() nounwind { 49 entry: 50 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ffqr_w_ARG1 51 %1 = tail call <4 x float> @llvm.mips.ffqr.w(<8 x i16> %0) 52 store <4 x float> %1, <4 x float>* @llvm_mips_ffqr_w_RES 53 ret void 54 } 55 56 declare <4 x float> @llvm.mips.ffqr.w(<8 x i16>) nounwind 57 58 ; CHECK: llvm_mips_ffqr_w_test: 59 ; CHECK: ld.h 60 ; CHECK: ffqr.w 61 ; CHECK: st.w 62 ; CHECK: .size llvm_mips_ffqr_w_test 63 ; 64 @llvm_mips_ffqr_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 65 @llvm_mips_ffqr_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16 66 67 define void @llvm_mips_ffqr_d_test() nounwind { 68 entry: 69 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ffqr_d_ARG1 70 %1 = tail call <2 x double> @llvm.mips.ffqr.d(<4 x i32> %0) 71 store <2 x double> %1, <2 x double>* @llvm_mips_ffqr_d_RES 72 ret void 73 } 74 75 declare <2 x double> @llvm.mips.ffqr.d(<4 x i32>) nounwind 76 77 ; CHECK: llvm_mips_ffqr_d_test: 78 ; CHECK: ld.w 79 ; CHECK: ffqr.d 80 ; CHECK: st.d 81 ; CHECK: .size llvm_mips_ffqr_d_test 82 ; 83
