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      1 ; Test the MSA floating-point to fixed-point conversion intrinsics that are
      2 ; encoded with the 2RF instruction format.
      3 
      4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
      5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
      6 
      7 @llvm_mips_ftq_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
      8 @llvm_mips_ftq_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
      9 @llvm_mips_ftq_h_RES  = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
     10 
     11 define void @llvm_mips_ftq_h_test() nounwind {
     12 entry:
     13   %0 = load <4 x float>, <4 x float>* @llvm_mips_ftq_h_ARG1
     14   %1 = load <4 x float>, <4 x float>* @llvm_mips_ftq_h_ARG2
     15   %2 = tail call <8 x i16> @llvm.mips.ftq.h(<4 x float> %0, <4 x float> %1)
     16   store <8 x i16> %2, <8 x i16>* @llvm_mips_ftq_h_RES
     17   ret void
     18 }
     19 
     20 declare <8 x i16> @llvm.mips.ftq.h(<4 x float>, <4 x float>) nounwind
     21 
     22 ; CHECK: llvm_mips_ftq_h_test:
     23 ; CHECK: ld.w
     24 ; CHECK: ld.w
     25 ; CHECK: ftq.h
     26 ; CHECK: st.h
     27 ; CHECK: .size llvm_mips_ftq_h_test
     28 ;
     29 @llvm_mips_ftq_w_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
     30 @llvm_mips_ftq_w_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
     31 @llvm_mips_ftq_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
     32 
     33 define void @llvm_mips_ftq_w_test() nounwind {
     34 entry:
     35   %0 = load <2 x double>, <2 x double>* @llvm_mips_ftq_w_ARG1
     36   %1 = load <2 x double>, <2 x double>* @llvm_mips_ftq_w_ARG2
     37   %2 = tail call <4 x i32> @llvm.mips.ftq.w(<2 x double> %0, <2 x double> %1)
     38   store <4 x i32> %2, <4 x i32>* @llvm_mips_ftq_w_RES
     39   ret void
     40 }
     41 
     42 declare <4 x i32> @llvm.mips.ftq.w(<2 x double>, <2 x double>) nounwind
     43 
     44 ; CHECK: llvm_mips_ftq_w_test:
     45 ; CHECK: ld.d
     46 ; CHECK: ld.d
     47 ; CHECK: ftq.w
     48 ; CHECK: st.w
     49 ; CHECK: .size llvm_mips_ftq_w_test
     50 ;
     51