1 ; Test the MSA intrinsics that are encoded with the 3R instruction format. 2 ; There are lots of these so this covers those beginning with 's' 3 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 6 7 @llvm_mips_sld_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 8 @llvm_mips_sld_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 9 @llvm_mips_sld_b_ARG3 = global i32 10, align 16 10 @llvm_mips_sld_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 11 12 define void @llvm_mips_sld_b_test() nounwind { 13 entry: 14 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sld_b_ARG1 15 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_sld_b_ARG2 16 %2 = load i32, i32* @llvm_mips_sld_b_ARG3 17 %3 = tail call <16 x i8> @llvm.mips.sld.b(<16 x i8> %0, <16 x i8> %1, i32 %2) 18 store <16 x i8> %3, <16 x i8>* @llvm_mips_sld_b_RES 19 ret void 20 } 21 22 declare <16 x i8> @llvm.mips.sld.b(<16 x i8>, <16 x i8>, i32) nounwind 23 24 ; CHECK: llvm_mips_sld_b_test: 25 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sld_b_ARG1) 26 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sld_b_ARG2) 27 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_sld_b_ARG3) 28 ; CHECK-DAG: ld.b [[WD:\$w[0-9]+]], 0([[R1]]) 29 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R2]]) 30 ; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R3]]) 31 ; CHECK-DAG: sld.b [[WD]], [[WS]]{{\[}}[[RT]]{{\]}} 32 ; CHECK-DAG: st.b [[WD]] 33 ; CHECK: .size llvm_mips_sld_b_test 34 ; 35 @llvm_mips_sld_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 36 @llvm_mips_sld_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 37 @llvm_mips_sld_h_ARG3 = global i32 10, align 16 38 @llvm_mips_sld_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 39 40 define void @llvm_mips_sld_h_test() nounwind { 41 entry: 42 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sld_h_ARG1 43 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_sld_h_ARG2 44 %2 = load i32, i32* @llvm_mips_sld_h_ARG3 45 %3 = tail call <8 x i16> @llvm.mips.sld.h(<8 x i16> %0, <8 x i16> %1, i32 %2) 46 store <8 x i16> %3, <8 x i16>* @llvm_mips_sld_h_RES 47 ret void 48 } 49 50 declare <8 x i16> @llvm.mips.sld.h(<8 x i16>, <8 x i16>, i32) nounwind 51 52 ; CHECK: llvm_mips_sld_h_test: 53 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sld_h_ARG1) 54 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sld_h_ARG2) 55 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_sld_h_ARG3) 56 ; CHECK-DAG: ld.h [[WD:\$w[0-9]+]], 0([[R1]]) 57 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R2]]) 58 ; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R3]]) 59 ; CHECK-DAG: sld.h [[WD]], [[WS]]{{\[}}[[RT]]{{\]}} 60 ; CHECK-DAG: st.h [[WD]] 61 ; CHECK: .size llvm_mips_sld_h_test 62 ; 63 @llvm_mips_sld_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 64 @llvm_mips_sld_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 65 @llvm_mips_sld_w_ARG3 = global i32 10, align 16 66 @llvm_mips_sld_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 67 68 define void @llvm_mips_sld_w_test() nounwind { 69 entry: 70 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sld_w_ARG1 71 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_sld_w_ARG2 72 %2 = load i32, i32* @llvm_mips_sld_w_ARG3 73 %3 = tail call <4 x i32> @llvm.mips.sld.w(<4 x i32> %0, <4 x i32> %1, i32 %2) 74 store <4 x i32> %3, <4 x i32>* @llvm_mips_sld_w_RES 75 ret void 76 } 77 78 declare <4 x i32> @llvm.mips.sld.w(<4 x i32>, <4 x i32>, i32) nounwind 79 80 ; CHECK: llvm_mips_sld_w_test: 81 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sld_w_ARG1) 82 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sld_w_ARG2) 83 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_sld_w_ARG3) 84 ; CHECK-DAG: ld.w [[WD:\$w[0-9]+]], 0([[R1]]) 85 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R2]]) 86 ; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R3]]) 87 ; CHECK-DAG: sld.w [[WD]], [[WS]]{{\[}}[[RT]]{{\]}} 88 ; CHECK-DAG: st.w [[WD]] 89 ; CHECK: .size llvm_mips_sld_w_test 90 ; 91 @llvm_mips_sld_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 92 @llvm_mips_sld_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 16 93 @llvm_mips_sld_d_ARG3 = global i32 10, align 16 94 @llvm_mips_sld_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 95 96 define void @llvm_mips_sld_d_test() nounwind { 97 entry: 98 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sld_d_ARG1 99 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_sld_d_ARG2 100 %2 = load i32, i32* @llvm_mips_sld_d_ARG3 101 %3 = tail call <2 x i64> @llvm.mips.sld.d(<2 x i64> %0, <2 x i64> %1, i32 %2) 102 store <2 x i64> %3, <2 x i64>* @llvm_mips_sld_d_RES 103 ret void 104 } 105 106 declare <2 x i64> @llvm.mips.sld.d(<2 x i64>, <2 x i64>, i32) nounwind 107 108 ; CHECK: llvm_mips_sld_d_test: 109 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sld_d_ARG1) 110 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sld_d_ARG2) 111 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_sld_d_ARG3) 112 ; CHECK-DAG: ld.d [[WD:\$w[0-9]+]], 0([[R1]]) 113 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R2]]) 114 ; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R3]]) 115 ; CHECK-DAG: sld.d [[WD]], [[WS]]{{\[}}[[RT]]{{\]}} 116 ; CHECK-DAG: st.d [[WD]] 117 ; CHECK: .size llvm_mips_sld_d_test 118 ; 119 @llvm_mips_sll_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 120 @llvm_mips_sll_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 121 @llvm_mips_sll_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 122 123 define void @llvm_mips_sll_b_test() nounwind { 124 entry: 125 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sll_b_ARG1 126 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_sll_b_ARG2 127 %2 = tail call <16 x i8> @llvm.mips.sll.b(<16 x i8> %0, <16 x i8> %1) 128 store <16 x i8> %2, <16 x i8>* @llvm_mips_sll_b_RES 129 ret void 130 } 131 132 declare <16 x i8> @llvm.mips.sll.b(<16 x i8>, <16 x i8>) nounwind 133 134 ; CHECK: llvm_mips_sll_b_test: 135 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_b_ARG1) 136 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_b_ARG2) 137 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 138 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 139 ; CHECK-DAG: sll.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 140 ; CHECK-DAG: st.b [[WD]] 141 ; CHECK: .size llvm_mips_sll_b_test 142 ; 143 @llvm_mips_sll_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 144 @llvm_mips_sll_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 145 @llvm_mips_sll_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 146 147 define void @llvm_mips_sll_h_test() nounwind { 148 entry: 149 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sll_h_ARG1 150 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_sll_h_ARG2 151 %2 = tail call <8 x i16> @llvm.mips.sll.h(<8 x i16> %0, <8 x i16> %1) 152 store <8 x i16> %2, <8 x i16>* @llvm_mips_sll_h_RES 153 ret void 154 } 155 156 declare <8 x i16> @llvm.mips.sll.h(<8 x i16>, <8 x i16>) nounwind 157 158 ; CHECK: llvm_mips_sll_h_test: 159 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_h_ARG1) 160 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_h_ARG2) 161 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 162 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 163 ; CHECK-DAG: sll.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 164 ; CHECK-DAG: st.h [[WD]] 165 ; CHECK: .size llvm_mips_sll_h_test 166 ; 167 @llvm_mips_sll_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 168 @llvm_mips_sll_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 169 @llvm_mips_sll_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 170 171 define void @llvm_mips_sll_w_test() nounwind { 172 entry: 173 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sll_w_ARG1 174 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_sll_w_ARG2 175 %2 = tail call <4 x i32> @llvm.mips.sll.w(<4 x i32> %0, <4 x i32> %1) 176 store <4 x i32> %2, <4 x i32>* @llvm_mips_sll_w_RES 177 ret void 178 } 179 180 declare <4 x i32> @llvm.mips.sll.w(<4 x i32>, <4 x i32>) nounwind 181 182 ; CHECK: llvm_mips_sll_w_test: 183 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_w_ARG1) 184 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_w_ARG2) 185 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 186 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 187 ; CHECK-DAG: sll.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 188 ; CHECK-DAG: st.w [[WD]] 189 ; CHECK: .size llvm_mips_sll_w_test 190 ; 191 @llvm_mips_sll_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 192 @llvm_mips_sll_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 193 @llvm_mips_sll_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 194 195 define void @llvm_mips_sll_d_test() nounwind { 196 entry: 197 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sll_d_ARG1 198 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_sll_d_ARG2 199 %2 = tail call <2 x i64> @llvm.mips.sll.d(<2 x i64> %0, <2 x i64> %1) 200 store <2 x i64> %2, <2 x i64>* @llvm_mips_sll_d_RES 201 ret void 202 } 203 204 declare <2 x i64> @llvm.mips.sll.d(<2 x i64>, <2 x i64>) nounwind 205 206 ; CHECK: llvm_mips_sll_d_test: 207 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_d_ARG1) 208 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_d_ARG2) 209 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 210 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 211 ; CHECK-DAG: sll.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 212 ; CHECK-DAG: st.d [[WD]] 213 ; CHECK: .size llvm_mips_sll_d_test 214 215 define void @sll_b_test() nounwind { 216 entry: 217 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sll_b_ARG1 218 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_sll_b_ARG2 219 %2 = shl <16 x i8> %0, %1 220 store <16 x i8> %2, <16 x i8>* @llvm_mips_sll_b_RES 221 ret void 222 } 223 224 ; CHECK: sll_b_test: 225 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_b_ARG1) 226 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_b_ARG2) 227 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 228 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 229 ; CHECK-DAG: sll.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 230 ; CHECK-DAG: st.b [[WD]] 231 ; CHECK: .size sll_b_test 232 233 define void @sll_h_test() nounwind { 234 entry: 235 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sll_h_ARG1 236 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_sll_h_ARG2 237 %2 = shl <8 x i16> %0, %1 238 store <8 x i16> %2, <8 x i16>* @llvm_mips_sll_h_RES 239 ret void 240 } 241 242 ; CHECK: sll_h_test: 243 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_h_ARG1) 244 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_h_ARG2) 245 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 246 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 247 ; CHECK-DAG: sll.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 248 ; CHECK-DAG: st.h [[WD]] 249 ; CHECK: .size sll_h_test 250 251 define void @sll_w_test() nounwind { 252 entry: 253 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sll_w_ARG1 254 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_sll_w_ARG2 255 %2 = shl <4 x i32> %0, %1 256 store <4 x i32> %2, <4 x i32>* @llvm_mips_sll_w_RES 257 ret void 258 } 259 260 ; CHECK: sll_w_test: 261 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_w_ARG1) 262 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_w_ARG2) 263 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 264 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 265 ; CHECK-DAG: sll.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 266 ; CHECK-DAG: st.w [[WD]] 267 ; CHECK: .size sll_w_test 268 269 define void @sll_d_test() nounwind { 270 entry: 271 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sll_d_ARG1 272 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_sll_d_ARG2 273 %2 = shl <2 x i64> %0, %1 274 store <2 x i64> %2, <2 x i64>* @llvm_mips_sll_d_RES 275 ret void 276 } 277 278 ; CHECK: sll_d_test: 279 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_d_ARG1) 280 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_d_ARG2) 281 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 282 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 283 ; CHECK-DAG: sll.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 284 ; CHECK-DAG: st.d [[WD]] 285 ; CHECK: .size sll_d_test 286 ; 287 @llvm_mips_sra_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 288 @llvm_mips_sra_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 289 @llvm_mips_sra_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 290 291 define void @llvm_mips_sra_b_test() nounwind { 292 entry: 293 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sra_b_ARG1 294 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_sra_b_ARG2 295 %2 = tail call <16 x i8> @llvm.mips.sra.b(<16 x i8> %0, <16 x i8> %1) 296 store <16 x i8> %2, <16 x i8>* @llvm_mips_sra_b_RES 297 ret void 298 } 299 300 declare <16 x i8> @llvm.mips.sra.b(<16 x i8>, <16 x i8>) nounwind 301 302 ; CHECK: llvm_mips_sra_b_test: 303 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_b_ARG1) 304 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_b_ARG2) 305 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 306 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 307 ; CHECK-DAG: sra.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 308 ; CHECK-DAG: st.b [[WD]] 309 ; CHECK: .size llvm_mips_sra_b_test 310 ; 311 @llvm_mips_sra_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 312 @llvm_mips_sra_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 313 @llvm_mips_sra_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 314 315 define void @llvm_mips_sra_h_test() nounwind { 316 entry: 317 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sra_h_ARG1 318 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_sra_h_ARG2 319 %2 = tail call <8 x i16> @llvm.mips.sra.h(<8 x i16> %0, <8 x i16> %1) 320 store <8 x i16> %2, <8 x i16>* @llvm_mips_sra_h_RES 321 ret void 322 } 323 324 declare <8 x i16> @llvm.mips.sra.h(<8 x i16>, <8 x i16>) nounwind 325 326 ; CHECK: llvm_mips_sra_h_test: 327 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_h_ARG1) 328 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_h_ARG2) 329 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 330 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 331 ; CHECK-DAG: sra.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 332 ; CHECK-DAG: st.h [[WD]] 333 ; CHECK: .size llvm_mips_sra_h_test 334 ; 335 @llvm_mips_sra_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 336 @llvm_mips_sra_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 337 @llvm_mips_sra_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 338 339 define void @llvm_mips_sra_w_test() nounwind { 340 entry: 341 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sra_w_ARG1 342 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_sra_w_ARG2 343 %2 = tail call <4 x i32> @llvm.mips.sra.w(<4 x i32> %0, <4 x i32> %1) 344 store <4 x i32> %2, <4 x i32>* @llvm_mips_sra_w_RES 345 ret void 346 } 347 348 declare <4 x i32> @llvm.mips.sra.w(<4 x i32>, <4 x i32>) nounwind 349 350 ; CHECK: llvm_mips_sra_w_test: 351 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_w_ARG1) 352 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_w_ARG2) 353 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 354 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 355 ; CHECK-DAG: sra.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 356 ; CHECK-DAG: st.w [[WD]] 357 ; CHECK: .size llvm_mips_sra_w_test 358 ; 359 @llvm_mips_sra_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 360 @llvm_mips_sra_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 361 @llvm_mips_sra_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 362 363 define void @llvm_mips_sra_d_test() nounwind { 364 entry: 365 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sra_d_ARG1 366 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_sra_d_ARG2 367 %2 = tail call <2 x i64> @llvm.mips.sra.d(<2 x i64> %0, <2 x i64> %1) 368 store <2 x i64> %2, <2 x i64>* @llvm_mips_sra_d_RES 369 ret void 370 } 371 372 declare <2 x i64> @llvm.mips.sra.d(<2 x i64>, <2 x i64>) nounwind 373 374 ; CHECK: llvm_mips_sra_d_test: 375 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_d_ARG1) 376 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_d_ARG2) 377 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 378 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 379 ; CHECK-DAG: sra.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 380 ; CHECK-DAG: st.d [[WD]] 381 ; CHECK: .size llvm_mips_sra_d_test 382 ; 383 384 define void @sra_b_test() nounwind { 385 entry: 386 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sra_b_ARG1 387 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_sra_b_ARG2 388 %2 = ashr <16 x i8> %0, %1 389 store <16 x i8> %2, <16 x i8>* @llvm_mips_sra_b_RES 390 ret void 391 } 392 393 ; CHECK: sra_b_test: 394 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_b_ARG1) 395 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_b_ARG2) 396 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 397 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 398 ; CHECK-DAG: sra.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 399 ; CHECK-DAG: st.b [[WD]] 400 ; CHECK: .size sra_b_test 401 402 define void @sra_h_test() nounwind { 403 entry: 404 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sra_h_ARG1 405 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_sra_h_ARG2 406 %2 = ashr <8 x i16> %0, %1 407 store <8 x i16> %2, <8 x i16>* @llvm_mips_sra_h_RES 408 ret void 409 } 410 411 ; CHECK: sra_h_test: 412 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_h_ARG1) 413 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_h_ARG2) 414 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 415 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 416 ; CHECK-DAG: sra.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 417 ; CHECK-DAG: st.h [[WD]] 418 ; CHECK: .size sra_h_test 419 420 define void @sra_w_test() nounwind { 421 entry: 422 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sra_w_ARG1 423 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_sra_w_ARG2 424 %2 = ashr <4 x i32> %0, %1 425 store <4 x i32> %2, <4 x i32>* @llvm_mips_sra_w_RES 426 ret void 427 } 428 429 ; CHECK: sra_w_test: 430 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_w_ARG1) 431 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_w_ARG2) 432 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 433 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 434 ; CHECK-DAG: sra.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 435 ; CHECK-DAG: st.w [[WD]] 436 ; CHECK: .size sra_w_test 437 438 define void @sra_d_test() nounwind { 439 entry: 440 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sra_d_ARG1 441 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_sra_d_ARG2 442 %2 = ashr <2 x i64> %0, %1 443 store <2 x i64> %2, <2 x i64>* @llvm_mips_sra_d_RES 444 ret void 445 } 446 447 ; CHECK: sra_d_test: 448 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_d_ARG1) 449 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_d_ARG2) 450 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 451 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 452 ; CHECK-DAG: sra.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 453 ; CHECK-DAG: st.d [[WD]] 454 ; CHECK: .size sra_d_test 455 456 @llvm_mips_srar_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 457 @llvm_mips_srar_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 458 @llvm_mips_srar_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 459 460 define void @llvm_mips_srar_b_test() nounwind { 461 entry: 462 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_srar_b_ARG1 463 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_srar_b_ARG2 464 %2 = tail call <16 x i8> @llvm.mips.srar.b(<16 x i8> %0, <16 x i8> %1) 465 store <16 x i8> %2, <16 x i8>* @llvm_mips_srar_b_RES 466 ret void 467 } 468 469 declare <16 x i8> @llvm.mips.srar.b(<16 x i8>, <16 x i8>) nounwind 470 471 ; CHECK: llvm_mips_srar_b_test: 472 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srar_b_ARG1) 473 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srar_b_ARG2) 474 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 475 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 476 ; CHECK-DAG: srar.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 477 ; CHECK-DAG: st.b [[WD]] 478 ; CHECK: .size llvm_mips_srar_b_test 479 ; 480 @llvm_mips_srar_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 481 @llvm_mips_srar_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 482 @llvm_mips_srar_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 483 484 define void @llvm_mips_srar_h_test() nounwind { 485 entry: 486 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_srar_h_ARG1 487 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_srar_h_ARG2 488 %2 = tail call <8 x i16> @llvm.mips.srar.h(<8 x i16> %0, <8 x i16> %1) 489 store <8 x i16> %2, <8 x i16>* @llvm_mips_srar_h_RES 490 ret void 491 } 492 493 declare <8 x i16> @llvm.mips.srar.h(<8 x i16>, <8 x i16>) nounwind 494 495 ; CHECK: llvm_mips_srar_h_test: 496 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srar_h_ARG1) 497 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srar_h_ARG2) 498 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 499 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 500 ; CHECK-DAG: srar.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 501 ; CHECK-DAG: st.h [[WD]] 502 ; CHECK: .size llvm_mips_srar_h_test 503 ; 504 @llvm_mips_srar_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 505 @llvm_mips_srar_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 506 @llvm_mips_srar_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 507 508 define void @llvm_mips_srar_w_test() nounwind { 509 entry: 510 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_srar_w_ARG1 511 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_srar_w_ARG2 512 %2 = tail call <4 x i32> @llvm.mips.srar.w(<4 x i32> %0, <4 x i32> %1) 513 store <4 x i32> %2, <4 x i32>* @llvm_mips_srar_w_RES 514 ret void 515 } 516 517 declare <4 x i32> @llvm.mips.srar.w(<4 x i32>, <4 x i32>) nounwind 518 519 ; CHECK: llvm_mips_srar_w_test: 520 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srar_w_ARG1) 521 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srar_w_ARG2) 522 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 523 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 524 ; CHECK-DAG: srar.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 525 ; CHECK-DAG: st.w [[WD]] 526 ; CHECK: .size llvm_mips_srar_w_test 527 ; 528 @llvm_mips_srar_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 529 @llvm_mips_srar_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 530 @llvm_mips_srar_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 531 532 define void @llvm_mips_srar_d_test() nounwind { 533 entry: 534 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_srar_d_ARG1 535 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_srar_d_ARG2 536 %2 = tail call <2 x i64> @llvm.mips.srar.d(<2 x i64> %0, <2 x i64> %1) 537 store <2 x i64> %2, <2 x i64>* @llvm_mips_srar_d_RES 538 ret void 539 } 540 541 declare <2 x i64> @llvm.mips.srar.d(<2 x i64>, <2 x i64>) nounwind 542 543 ; CHECK: llvm_mips_srar_d_test: 544 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srar_d_ARG1) 545 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srar_d_ARG2) 546 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 547 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 548 ; CHECK-DAG: srar.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 549 ; CHECK-DAG: st.d [[WD]] 550 ; CHECK: .size llvm_mips_srar_d_test 551 ; 552 @llvm_mips_srl_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 553 @llvm_mips_srl_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 554 @llvm_mips_srl_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 555 556 define void @llvm_mips_srl_b_test() nounwind { 557 entry: 558 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_srl_b_ARG1 559 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_srl_b_ARG2 560 %2 = tail call <16 x i8> @llvm.mips.srl.b(<16 x i8> %0, <16 x i8> %1) 561 store <16 x i8> %2, <16 x i8>* @llvm_mips_srl_b_RES 562 ret void 563 } 564 565 declare <16 x i8> @llvm.mips.srl.b(<16 x i8>, <16 x i8>) nounwind 566 567 ; CHECK: llvm_mips_srl_b_test: 568 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_b_ARG1) 569 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_b_ARG2) 570 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 571 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 572 ; CHECK-DAG: srl.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 573 ; CHECK-DAG: st.b [[WD]] 574 ; CHECK: .size llvm_mips_srl_b_test 575 ; 576 @llvm_mips_srl_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 577 @llvm_mips_srl_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 578 @llvm_mips_srl_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 579 580 define void @llvm_mips_srl_h_test() nounwind { 581 entry: 582 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_srl_h_ARG1 583 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_srl_h_ARG2 584 %2 = tail call <8 x i16> @llvm.mips.srl.h(<8 x i16> %0, <8 x i16> %1) 585 store <8 x i16> %2, <8 x i16>* @llvm_mips_srl_h_RES 586 ret void 587 } 588 589 declare <8 x i16> @llvm.mips.srl.h(<8 x i16>, <8 x i16>) nounwind 590 591 ; CHECK: llvm_mips_srl_h_test: 592 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_h_ARG1) 593 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_h_ARG2) 594 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 595 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 596 ; CHECK-DAG: srl.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 597 ; CHECK-DAG: st.h [[WD]] 598 ; CHECK: .size llvm_mips_srl_h_test 599 ; 600 @llvm_mips_srl_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 601 @llvm_mips_srl_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 602 @llvm_mips_srl_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 603 604 define void @llvm_mips_srl_w_test() nounwind { 605 entry: 606 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_srl_w_ARG1 607 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_srl_w_ARG2 608 %2 = tail call <4 x i32> @llvm.mips.srl.w(<4 x i32> %0, <4 x i32> %1) 609 store <4 x i32> %2, <4 x i32>* @llvm_mips_srl_w_RES 610 ret void 611 } 612 613 declare <4 x i32> @llvm.mips.srl.w(<4 x i32>, <4 x i32>) nounwind 614 615 ; CHECK: llvm_mips_srl_w_test: 616 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_w_ARG1) 617 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_w_ARG2) 618 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 619 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 620 ; CHECK-DAG: srl.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 621 ; CHECK-DAG: st.w [[WD]] 622 ; CHECK: .size llvm_mips_srl_w_test 623 ; 624 @llvm_mips_srl_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 625 @llvm_mips_srl_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 626 @llvm_mips_srl_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 627 628 define void @llvm_mips_srl_d_test() nounwind { 629 entry: 630 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_srl_d_ARG1 631 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_srl_d_ARG2 632 %2 = tail call <2 x i64> @llvm.mips.srl.d(<2 x i64> %0, <2 x i64> %1) 633 store <2 x i64> %2, <2 x i64>* @llvm_mips_srl_d_RES 634 ret void 635 } 636 637 declare <2 x i64> @llvm.mips.srl.d(<2 x i64>, <2 x i64>) nounwind 638 639 ; CHECK: llvm_mips_srl_d_test: 640 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_d_ARG1) 641 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_d_ARG2) 642 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 643 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 644 ; CHECK-DAG: srl.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 645 ; CHECK-DAG: st.d [[WD]] 646 ; CHECK: .size llvm_mips_srl_d_test 647 ; 648 @llvm_mips_srlr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 649 @llvm_mips_srlr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 650 @llvm_mips_srlr_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 651 652 define void @llvm_mips_srlr_b_test() nounwind { 653 entry: 654 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_srlr_b_ARG1 655 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_srlr_b_ARG2 656 %2 = tail call <16 x i8> @llvm.mips.srlr.b(<16 x i8> %0, <16 x i8> %1) 657 store <16 x i8> %2, <16 x i8>* @llvm_mips_srlr_b_RES 658 ret void 659 } 660 661 declare <16 x i8> @llvm.mips.srlr.b(<16 x i8>, <16 x i8>) nounwind 662 663 ; CHECK: llvm_mips_srlr_b_test: 664 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srlr_b_ARG1) 665 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srlr_b_ARG2) 666 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 667 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 668 ; CHECK-DAG: srlr.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 669 ; CHECK-DAG: st.b [[WD]] 670 ; CHECK: .size llvm_mips_srlr_b_test 671 ; 672 @llvm_mips_srlr_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 673 @llvm_mips_srlr_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 674 @llvm_mips_srlr_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 675 676 define void @llvm_mips_srlr_h_test() nounwind { 677 entry: 678 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_srlr_h_ARG1 679 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_srlr_h_ARG2 680 %2 = tail call <8 x i16> @llvm.mips.srlr.h(<8 x i16> %0, <8 x i16> %1) 681 store <8 x i16> %2, <8 x i16>* @llvm_mips_srlr_h_RES 682 ret void 683 } 684 685 declare <8 x i16> @llvm.mips.srlr.h(<8 x i16>, <8 x i16>) nounwind 686 687 ; CHECK: llvm_mips_srlr_h_test: 688 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srlr_h_ARG1) 689 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srlr_h_ARG2) 690 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 691 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 692 ; CHECK-DAG: srlr.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 693 ; CHECK-DAG: st.h [[WD]] 694 ; CHECK: .size llvm_mips_srlr_h_test 695 ; 696 @llvm_mips_srlr_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 697 @llvm_mips_srlr_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 698 @llvm_mips_srlr_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 699 700 define void @llvm_mips_srlr_w_test() nounwind { 701 entry: 702 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_srlr_w_ARG1 703 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_srlr_w_ARG2 704 %2 = tail call <4 x i32> @llvm.mips.srlr.w(<4 x i32> %0, <4 x i32> %1) 705 store <4 x i32> %2, <4 x i32>* @llvm_mips_srlr_w_RES 706 ret void 707 } 708 709 declare <4 x i32> @llvm.mips.srlr.w(<4 x i32>, <4 x i32>) nounwind 710 711 ; CHECK: llvm_mips_srlr_w_test: 712 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srlr_w_ARG1) 713 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srlr_w_ARG2) 714 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 715 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 716 ; CHECK-DAG: srlr.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 717 ; CHECK-DAG: st.w [[WD]] 718 ; CHECK: .size llvm_mips_srlr_w_test 719 ; 720 @llvm_mips_srlr_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 721 @llvm_mips_srlr_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 722 @llvm_mips_srlr_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 723 724 define void @llvm_mips_srlr_d_test() nounwind { 725 entry: 726 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_srlr_d_ARG1 727 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_srlr_d_ARG2 728 %2 = tail call <2 x i64> @llvm.mips.srlr.d(<2 x i64> %0, <2 x i64> %1) 729 store <2 x i64> %2, <2 x i64>* @llvm_mips_srlr_d_RES 730 ret void 731 } 732 733 declare <2 x i64> @llvm.mips.srlr.d(<2 x i64>, <2 x i64>) nounwind 734 735 ; CHECK: llvm_mips_srlr_d_test: 736 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srlr_d_ARG1) 737 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srlr_d_ARG2) 738 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 739 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 740 ; CHECK-DAG: srlr.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 741 ; CHECK-DAG: st.d [[WD]] 742 ; CHECK: .size llvm_mips_srlr_d_test 743 ; 744 745 define void @srl_b_test() nounwind { 746 entry: 747 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_srl_b_ARG1 748 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_srl_b_ARG2 749 %2 = lshr <16 x i8> %0, %1 750 store <16 x i8> %2, <16 x i8>* @llvm_mips_srl_b_RES 751 ret void 752 } 753 754 ; CHECK: srl_b_test: 755 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_b_ARG1) 756 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_b_ARG2) 757 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 758 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 759 ; CHECK-DAG: srl.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 760 ; CHECK-DAG: st.b [[WD]] 761 ; CHECK: .size srl_b_test 762 763 define void @srl_h_test() nounwind { 764 entry: 765 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_srl_h_ARG1 766 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_srl_h_ARG2 767 %2 = lshr <8 x i16> %0, %1 768 store <8 x i16> %2, <8 x i16>* @llvm_mips_srl_h_RES 769 ret void 770 } 771 772 ; CHECK: srl_h_test: 773 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_h_ARG1) 774 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_h_ARG2) 775 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 776 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 777 ; CHECK-DAG: srl.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 778 ; CHECK-DAG: st.h [[WD]] 779 ; CHECK: .size srl_h_test 780 781 define void @srl_w_test() nounwind { 782 entry: 783 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_srl_w_ARG1 784 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_srl_w_ARG2 785 %2 = lshr <4 x i32> %0, %1 786 store <4 x i32> %2, <4 x i32>* @llvm_mips_srl_w_RES 787 ret void 788 } 789 790 ; CHECK: srl_w_test: 791 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_w_ARG1) 792 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_w_ARG2) 793 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 794 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 795 ; CHECK-DAG: srl.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 796 ; CHECK-DAG: st.w [[WD]] 797 ; CHECK: .size srl_w_test 798 799 define void @srl_d_test() nounwind { 800 entry: 801 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_srl_d_ARG1 802 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_srl_d_ARG2 803 %2 = lshr <2 x i64> %0, %1 804 store <2 x i64> %2, <2 x i64>* @llvm_mips_srl_d_RES 805 ret void 806 } 807 808 ; CHECK: srl_d_test: 809 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_d_ARG1) 810 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_d_ARG2) 811 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 812 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 813 ; CHECK-DAG: srl.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 814 ; CHECK-DAG: st.d [[WD]] 815 ; CHECK: .size srl_d_test 816 817 @llvm_mips_subs_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 818 @llvm_mips_subs_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 819 @llvm_mips_subs_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 820 821 define void @llvm_mips_subs_s_b_test() nounwind { 822 entry: 823 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_subs_s_b_ARG1 824 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_subs_s_b_ARG2 825 %2 = tail call <16 x i8> @llvm.mips.subs.s.b(<16 x i8> %0, <16 x i8> %1) 826 store <16 x i8> %2, <16 x i8>* @llvm_mips_subs_s_b_RES 827 ret void 828 } 829 830 declare <16 x i8> @llvm.mips.subs.s.b(<16 x i8>, <16 x i8>) nounwind 831 832 ; CHECK: llvm_mips_subs_s_b_test: 833 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subs_s_b_ARG1) 834 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subs_s_b_ARG2) 835 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 836 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 837 ; CHECK-DAG: subs_s.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 838 ; CHECK-DAG: st.b [[WD]] 839 ; CHECK: .size llvm_mips_subs_s_b_test 840 ; 841 @llvm_mips_subs_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 842 @llvm_mips_subs_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 843 @llvm_mips_subs_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 844 845 define void @llvm_mips_subs_s_h_test() nounwind { 846 entry: 847 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_subs_s_h_ARG1 848 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_subs_s_h_ARG2 849 %2 = tail call <8 x i16> @llvm.mips.subs.s.h(<8 x i16> %0, <8 x i16> %1) 850 store <8 x i16> %2, <8 x i16>* @llvm_mips_subs_s_h_RES 851 ret void 852 } 853 854 declare <8 x i16> @llvm.mips.subs.s.h(<8 x i16>, <8 x i16>) nounwind 855 856 ; CHECK: llvm_mips_subs_s_h_test: 857 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subs_s_h_ARG1) 858 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subs_s_h_ARG2) 859 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 860 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 861 ; CHECK-DAG: subs_s.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 862 ; CHECK-DAG: st.h [[WD]] 863 ; CHECK: .size llvm_mips_subs_s_h_test 864 ; 865 @llvm_mips_subs_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 866 @llvm_mips_subs_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 867 @llvm_mips_subs_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 868 869 define void @llvm_mips_subs_s_w_test() nounwind { 870 entry: 871 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_subs_s_w_ARG1 872 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_subs_s_w_ARG2 873 %2 = tail call <4 x i32> @llvm.mips.subs.s.w(<4 x i32> %0, <4 x i32> %1) 874 store <4 x i32> %2, <4 x i32>* @llvm_mips_subs_s_w_RES 875 ret void 876 } 877 878 declare <4 x i32> @llvm.mips.subs.s.w(<4 x i32>, <4 x i32>) nounwind 879 880 ; CHECK: llvm_mips_subs_s_w_test: 881 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subs_s_w_ARG1) 882 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subs_s_w_ARG2) 883 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 884 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 885 ; CHECK-DAG: subs_s.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 886 ; CHECK-DAG: st.w [[WD]] 887 ; CHECK: .size llvm_mips_subs_s_w_test 888 ; 889 @llvm_mips_subs_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 890 @llvm_mips_subs_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 891 @llvm_mips_subs_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 892 893 define void @llvm_mips_subs_s_d_test() nounwind { 894 entry: 895 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_subs_s_d_ARG1 896 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_subs_s_d_ARG2 897 %2 = tail call <2 x i64> @llvm.mips.subs.s.d(<2 x i64> %0, <2 x i64> %1) 898 store <2 x i64> %2, <2 x i64>* @llvm_mips_subs_s_d_RES 899 ret void 900 } 901 902 declare <2 x i64> @llvm.mips.subs.s.d(<2 x i64>, <2 x i64>) nounwind 903 904 ; CHECK: llvm_mips_subs_s_d_test: 905 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subs_s_d_ARG1) 906 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subs_s_d_ARG2) 907 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 908 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 909 ; CHECK-DAG: subs_s.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 910 ; CHECK-DAG: st.d [[WD]] 911 ; CHECK: .size llvm_mips_subs_s_d_test 912 ; 913 @llvm_mips_subs_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 914 @llvm_mips_subs_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 915 @llvm_mips_subs_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 916 917 define void @llvm_mips_subs_u_b_test() nounwind { 918 entry: 919 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_subs_u_b_ARG1 920 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_subs_u_b_ARG2 921 %2 = tail call <16 x i8> @llvm.mips.subs.u.b(<16 x i8> %0, <16 x i8> %1) 922 store <16 x i8> %2, <16 x i8>* @llvm_mips_subs_u_b_RES 923 ret void 924 } 925 926 declare <16 x i8> @llvm.mips.subs.u.b(<16 x i8>, <16 x i8>) nounwind 927 928 ; CHECK: llvm_mips_subs_u_b_test: 929 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subs_u_b_ARG1) 930 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subs_u_b_ARG2) 931 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 932 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 933 ; CHECK-DAG: subs_u.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 934 ; CHECK-DAG: st.b [[WD]] 935 ; CHECK: .size llvm_mips_subs_u_b_test 936 ; 937 @llvm_mips_subs_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 938 @llvm_mips_subs_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 939 @llvm_mips_subs_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 940 941 define void @llvm_mips_subs_u_h_test() nounwind { 942 entry: 943 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_subs_u_h_ARG1 944 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_subs_u_h_ARG2 945 %2 = tail call <8 x i16> @llvm.mips.subs.u.h(<8 x i16> %0, <8 x i16> %1) 946 store <8 x i16> %2, <8 x i16>* @llvm_mips_subs_u_h_RES 947 ret void 948 } 949 950 declare <8 x i16> @llvm.mips.subs.u.h(<8 x i16>, <8 x i16>) nounwind 951 952 ; CHECK: llvm_mips_subs_u_h_test: 953 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subs_u_h_ARG1) 954 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subs_u_h_ARG2) 955 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 956 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 957 ; CHECK-DAG: subs_u.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 958 ; CHECK-DAG: st.h [[WD]] 959 ; CHECK: .size llvm_mips_subs_u_h_test 960 ; 961 @llvm_mips_subs_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 962 @llvm_mips_subs_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 963 @llvm_mips_subs_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 964 965 define void @llvm_mips_subs_u_w_test() nounwind { 966 entry: 967 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_subs_u_w_ARG1 968 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_subs_u_w_ARG2 969 %2 = tail call <4 x i32> @llvm.mips.subs.u.w(<4 x i32> %0, <4 x i32> %1) 970 store <4 x i32> %2, <4 x i32>* @llvm_mips_subs_u_w_RES 971 ret void 972 } 973 974 declare <4 x i32> @llvm.mips.subs.u.w(<4 x i32>, <4 x i32>) nounwind 975 976 ; CHECK: llvm_mips_subs_u_w_test: 977 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subs_u_w_ARG1) 978 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subs_u_w_ARG2) 979 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 980 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 981 ; CHECK-DAG: subs_u.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 982 ; CHECK-DAG: st.w [[WD]] 983 ; CHECK: .size llvm_mips_subs_u_w_test 984 ; 985 @llvm_mips_subs_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 986 @llvm_mips_subs_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 987 @llvm_mips_subs_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 988 989 define void @llvm_mips_subs_u_d_test() nounwind { 990 entry: 991 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_subs_u_d_ARG1 992 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_subs_u_d_ARG2 993 %2 = tail call <2 x i64> @llvm.mips.subs.u.d(<2 x i64> %0, <2 x i64> %1) 994 store <2 x i64> %2, <2 x i64>* @llvm_mips_subs_u_d_RES 995 ret void 996 } 997 998 declare <2 x i64> @llvm.mips.subs.u.d(<2 x i64>, <2 x i64>) nounwind 999 1000 ; CHECK: llvm_mips_subs_u_d_test: 1001 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subs_u_d_ARG1) 1002 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subs_u_d_ARG2) 1003 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 1004 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 1005 ; CHECK-DAG: subs_u.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1006 ; CHECK-DAG: st.d [[WD]] 1007 ; CHECK: .size llvm_mips_subs_u_d_test 1008 ; 1009 @llvm_mips_subsus_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 1010 @llvm_mips_subsus_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 1011 @llvm_mips_subsus_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 1012 1013 define void @llvm_mips_subsus_u_b_test() nounwind { 1014 entry: 1015 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_subsus_u_b_ARG1 1016 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_subsus_u_b_ARG2 1017 %2 = tail call <16 x i8> @llvm.mips.subsus.u.b(<16 x i8> %0, <16 x i8> %1) 1018 store <16 x i8> %2, <16 x i8>* @llvm_mips_subsus_u_b_RES 1019 ret void 1020 } 1021 1022 declare <16 x i8> @llvm.mips.subsus.u.b(<16 x i8>, <16 x i8>) nounwind 1023 1024 ; CHECK: llvm_mips_subsus_u_b_test: 1025 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subsus_u_b_ARG1) 1026 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subsus_u_b_ARG2) 1027 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 1028 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 1029 ; CHECK-DAG: subsus_u.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1030 ; CHECK-DAG: st.b [[WD]] 1031 ; CHECK: .size llvm_mips_subsus_u_b_test 1032 ; 1033 @llvm_mips_subsus_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 1034 @llvm_mips_subsus_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 1035 @llvm_mips_subsus_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 1036 1037 define void @llvm_mips_subsus_u_h_test() nounwind { 1038 entry: 1039 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_subsus_u_h_ARG1 1040 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_subsus_u_h_ARG2 1041 %2 = tail call <8 x i16> @llvm.mips.subsus.u.h(<8 x i16> %0, <8 x i16> %1) 1042 store <8 x i16> %2, <8 x i16>* @llvm_mips_subsus_u_h_RES 1043 ret void 1044 } 1045 1046 declare <8 x i16> @llvm.mips.subsus.u.h(<8 x i16>, <8 x i16>) nounwind 1047 1048 ; CHECK: llvm_mips_subsus_u_h_test: 1049 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subsus_u_h_ARG1) 1050 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subsus_u_h_ARG2) 1051 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 1052 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 1053 ; CHECK-DAG: subsus_u.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1054 ; CHECK-DAG: st.h [[WD]] 1055 ; CHECK: .size llvm_mips_subsus_u_h_test 1056 ; 1057 @llvm_mips_subsus_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 1058 @llvm_mips_subsus_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 1059 @llvm_mips_subsus_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 1060 1061 define void @llvm_mips_subsus_u_w_test() nounwind { 1062 entry: 1063 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_subsus_u_w_ARG1 1064 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_subsus_u_w_ARG2 1065 %2 = tail call <4 x i32> @llvm.mips.subsus.u.w(<4 x i32> %0, <4 x i32> %1) 1066 store <4 x i32> %2, <4 x i32>* @llvm_mips_subsus_u_w_RES 1067 ret void 1068 } 1069 1070 declare <4 x i32> @llvm.mips.subsus.u.w(<4 x i32>, <4 x i32>) nounwind 1071 1072 ; CHECK: llvm_mips_subsus_u_w_test: 1073 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subsus_u_w_ARG1) 1074 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subsus_u_w_ARG2) 1075 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 1076 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 1077 ; CHECK-DAG: subsus_u.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1078 ; CHECK-DAG: st.w [[WD]] 1079 ; CHECK: .size llvm_mips_subsus_u_w_test 1080 ; 1081 @llvm_mips_subsus_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 1082 @llvm_mips_subsus_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 1083 @llvm_mips_subsus_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 1084 1085 define void @llvm_mips_subsus_u_d_test() nounwind { 1086 entry: 1087 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_subsus_u_d_ARG1 1088 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_subsus_u_d_ARG2 1089 %2 = tail call <2 x i64> @llvm.mips.subsus.u.d(<2 x i64> %0, <2 x i64> %1) 1090 store <2 x i64> %2, <2 x i64>* @llvm_mips_subsus_u_d_RES 1091 ret void 1092 } 1093 1094 declare <2 x i64> @llvm.mips.subsus.u.d(<2 x i64>, <2 x i64>) nounwind 1095 1096 ; CHECK: llvm_mips_subsus_u_d_test: 1097 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subsus_u_d_ARG1) 1098 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subsus_u_d_ARG2) 1099 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 1100 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 1101 ; CHECK-DAG: subsus_u.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1102 ; CHECK-DAG: st.d [[WD]] 1103 ; CHECK: .size llvm_mips_subsus_u_d_test 1104 ; 1105 @llvm_mips_subsuu_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 1106 @llvm_mips_subsuu_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 1107 @llvm_mips_subsuu_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 1108 1109 define void @llvm_mips_subsuu_s_b_test() nounwind { 1110 entry: 1111 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_subsuu_s_b_ARG1 1112 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_subsuu_s_b_ARG2 1113 %2 = tail call <16 x i8> @llvm.mips.subsuu.s.b(<16 x i8> %0, <16 x i8> %1) 1114 store <16 x i8> %2, <16 x i8>* @llvm_mips_subsuu_s_b_RES 1115 ret void 1116 } 1117 1118 declare <16 x i8> @llvm.mips.subsuu.s.b(<16 x i8>, <16 x i8>) nounwind 1119 1120 ; CHECK: llvm_mips_subsuu_s_b_test: 1121 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subsuu_s_b_ARG1) 1122 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subsuu_s_b_ARG2) 1123 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 1124 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 1125 ; CHECK-DAG: subsuu_s.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1126 ; CHECK-DAG: st.b [[WD]] 1127 ; CHECK: .size llvm_mips_subsuu_s_b_test 1128 ; 1129 @llvm_mips_subsuu_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 1130 @llvm_mips_subsuu_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 1131 @llvm_mips_subsuu_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 1132 1133 define void @llvm_mips_subsuu_s_h_test() nounwind { 1134 entry: 1135 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_subsuu_s_h_ARG1 1136 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_subsuu_s_h_ARG2 1137 %2 = tail call <8 x i16> @llvm.mips.subsuu.s.h(<8 x i16> %0, <8 x i16> %1) 1138 store <8 x i16> %2, <8 x i16>* @llvm_mips_subsuu_s_h_RES 1139 ret void 1140 } 1141 1142 declare <8 x i16> @llvm.mips.subsuu.s.h(<8 x i16>, <8 x i16>) nounwind 1143 1144 ; CHECK: llvm_mips_subsuu_s_h_test: 1145 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subsuu_s_h_ARG1) 1146 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subsuu_s_h_ARG2) 1147 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 1148 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 1149 ; CHECK-DAG: subsuu_s.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1150 ; CHECK-DAG: st.h [[WD]] 1151 ; CHECK: .size llvm_mips_subsuu_s_h_test 1152 ; 1153 @llvm_mips_subsuu_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 1154 @llvm_mips_subsuu_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 1155 @llvm_mips_subsuu_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 1156 1157 define void @llvm_mips_subsuu_s_w_test() nounwind { 1158 entry: 1159 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_subsuu_s_w_ARG1 1160 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_subsuu_s_w_ARG2 1161 %2 = tail call <4 x i32> @llvm.mips.subsuu.s.w(<4 x i32> %0, <4 x i32> %1) 1162 store <4 x i32> %2, <4 x i32>* @llvm_mips_subsuu_s_w_RES 1163 ret void 1164 } 1165 1166 declare <4 x i32> @llvm.mips.subsuu.s.w(<4 x i32>, <4 x i32>) nounwind 1167 1168 ; CHECK: llvm_mips_subsuu_s_w_test: 1169 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subsuu_s_w_ARG1) 1170 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subsuu_s_w_ARG2) 1171 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 1172 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 1173 ; CHECK-DAG: subsuu_s.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1174 ; CHECK-DAG: st.w [[WD]] 1175 ; CHECK: .size llvm_mips_subsuu_s_w_test 1176 ; 1177 @llvm_mips_subsuu_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 1178 @llvm_mips_subsuu_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 1179 @llvm_mips_subsuu_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 1180 1181 define void @llvm_mips_subsuu_s_d_test() nounwind { 1182 entry: 1183 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_subsuu_s_d_ARG1 1184 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_subsuu_s_d_ARG2 1185 %2 = tail call <2 x i64> @llvm.mips.subsuu.s.d(<2 x i64> %0, <2 x i64> %1) 1186 store <2 x i64> %2, <2 x i64>* @llvm_mips_subsuu_s_d_RES 1187 ret void 1188 } 1189 1190 declare <2 x i64> @llvm.mips.subsuu.s.d(<2 x i64>, <2 x i64>) nounwind 1191 1192 ; CHECK: llvm_mips_subsuu_s_d_test: 1193 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subsuu_s_d_ARG1) 1194 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subsuu_s_d_ARG2) 1195 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 1196 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 1197 ; CHECK-DAG: subsuu_s.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1198 ; CHECK-DAG: st.d [[WD]] 1199 ; CHECK: .size llvm_mips_subsuu_s_d_test 1200 ; 1201 @llvm_mips_subv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 1202 @llvm_mips_subv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 1203 @llvm_mips_subv_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 1204 1205 define void @llvm_mips_subv_b_test() nounwind { 1206 entry: 1207 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_subv_b_ARG1 1208 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_subv_b_ARG2 1209 %2 = tail call <16 x i8> @llvm.mips.subv.b(<16 x i8> %0, <16 x i8> %1) 1210 store <16 x i8> %2, <16 x i8>* @llvm_mips_subv_b_RES 1211 ret void 1212 } 1213 1214 declare <16 x i8> @llvm.mips.subv.b(<16 x i8>, <16 x i8>) nounwind 1215 1216 ; CHECK: llvm_mips_subv_b_test: 1217 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subv_b_ARG1) 1218 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subv_b_ARG2) 1219 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 1220 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 1221 ; CHECK-DAG: subv.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1222 ; CHECK-DAG: st.b [[WD]] 1223 ; CHECK: .size llvm_mips_subv_b_test 1224 ; 1225 @llvm_mips_subv_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 1226 @llvm_mips_subv_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 1227 @llvm_mips_subv_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 1228 1229 define void @llvm_mips_subv_h_test() nounwind { 1230 entry: 1231 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_subv_h_ARG1 1232 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_subv_h_ARG2 1233 %2 = tail call <8 x i16> @llvm.mips.subv.h(<8 x i16> %0, <8 x i16> %1) 1234 store <8 x i16> %2, <8 x i16>* @llvm_mips_subv_h_RES 1235 ret void 1236 } 1237 1238 declare <8 x i16> @llvm.mips.subv.h(<8 x i16>, <8 x i16>) nounwind 1239 1240 ; CHECK: llvm_mips_subv_h_test: 1241 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subv_h_ARG1) 1242 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subv_h_ARG2) 1243 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 1244 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 1245 ; CHECK-DAG: subv.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1246 ; CHECK-DAG: st.h [[WD]] 1247 ; CHECK: .size llvm_mips_subv_h_test 1248 ; 1249 @llvm_mips_subv_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 1250 @llvm_mips_subv_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 1251 @llvm_mips_subv_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 1252 1253 define void @llvm_mips_subv_w_test() nounwind { 1254 entry: 1255 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_subv_w_ARG1 1256 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_subv_w_ARG2 1257 %2 = tail call <4 x i32> @llvm.mips.subv.w(<4 x i32> %0, <4 x i32> %1) 1258 store <4 x i32> %2, <4 x i32>* @llvm_mips_subv_w_RES 1259 ret void 1260 } 1261 1262 declare <4 x i32> @llvm.mips.subv.w(<4 x i32>, <4 x i32>) nounwind 1263 1264 ; CHECK: llvm_mips_subv_w_test: 1265 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subv_w_ARG1) 1266 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subv_w_ARG2) 1267 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 1268 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 1269 ; CHECK-DAG: subv.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1270 ; CHECK-DAG: st.w [[WD]] 1271 ; CHECK: .size llvm_mips_subv_w_test 1272 ; 1273 @llvm_mips_subv_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 1274 @llvm_mips_subv_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 1275 @llvm_mips_subv_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 1276 1277 define void @llvm_mips_subv_d_test() nounwind { 1278 entry: 1279 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_subv_d_ARG1 1280 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_subv_d_ARG2 1281 %2 = tail call <2 x i64> @llvm.mips.subv.d(<2 x i64> %0, <2 x i64> %1) 1282 store <2 x i64> %2, <2 x i64>* @llvm_mips_subv_d_RES 1283 ret void 1284 } 1285 1286 declare <2 x i64> @llvm.mips.subv.d(<2 x i64>, <2 x i64>) nounwind 1287 1288 ; CHECK: llvm_mips_subv_d_test: 1289 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subv_d_ARG1) 1290 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subv_d_ARG2) 1291 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 1292 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 1293 ; CHECK-DAG: subv.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1294 ; CHECK-DAG: st.d [[WD]] 1295 ; CHECK: .size llvm_mips_subv_d_test 1296 ; 1297 1298 define void @subv_b_test() nounwind { 1299 entry: 1300 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_subv_b_ARG1 1301 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_subv_b_ARG2 1302 %2 = sub <16 x i8> %0, %1 1303 store <16 x i8> %2, <16 x i8>* @llvm_mips_subv_b_RES 1304 ret void 1305 } 1306 1307 ; CHECK: subv_b_test: 1308 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subv_b_ARG1) 1309 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subv_b_ARG2) 1310 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 1311 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 1312 ; CHECK-DAG: subv.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1313 ; CHECK-DAG: st.b [[WD]] 1314 ; CHECK: .size subv_b_test 1315 1316 define void @subv_h_test() nounwind { 1317 entry: 1318 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_subv_h_ARG1 1319 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_subv_h_ARG2 1320 %2 = sub <8 x i16> %0, %1 1321 store <8 x i16> %2, <8 x i16>* @llvm_mips_subv_h_RES 1322 ret void 1323 } 1324 1325 ; CHECK: subv_h_test: 1326 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subv_h_ARG1) 1327 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subv_h_ARG2) 1328 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 1329 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 1330 ; CHECK-DAG: subv.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1331 ; CHECK-DAG: st.h [[WD]] 1332 ; CHECK: .size subv_h_test 1333 1334 define void @subv_w_test() nounwind { 1335 entry: 1336 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_subv_w_ARG1 1337 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_subv_w_ARG2 1338 %2 = sub <4 x i32> %0, %1 1339 store <4 x i32> %2, <4 x i32>* @llvm_mips_subv_w_RES 1340 ret void 1341 } 1342 1343 ; CHECK: subv_w_test: 1344 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subv_w_ARG1) 1345 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subv_w_ARG2) 1346 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 1347 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 1348 ; CHECK-DAG: subv.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1349 ; CHECK-DAG: st.w [[WD]] 1350 ; CHECK: .size subv_w_test 1351 1352 define void @subv_d_test() nounwind { 1353 entry: 1354 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_subv_d_ARG1 1355 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_subv_d_ARG2 1356 %2 = sub <2 x i64> %0, %1 1357 store <2 x i64> %2, <2 x i64>* @llvm_mips_subv_d_RES 1358 ret void 1359 } 1360 1361 ; CHECK: subv_d_test: 1362 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subv_d_ARG1) 1363 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subv_d_ARG2) 1364 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 1365 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 1366 ; CHECK-DAG: subv.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1367 ; CHECK-DAG: st.d [[WD]] 1368 ; CHECK: .size subv_d_test 1369 ; 1370
