1 ; Test the MSA intrinsics that are encoded with the SPECIAL instruction format. 2 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \ 4 ; RUN: FileCheck %s --check-prefix=MIPS32 5 ; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ 6 ; RUN: FileCheck %s --check-prefix=MIPS64 7 ; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa < %s | \ 8 ; RUN: FileCheck %s --check-prefix=MIPS32 9 ; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+msa < %s | \ 10 ; RUN: FileCheck %s --check-prefix=MIPS64 11 12 define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind { 13 entry: 14 %0 = tail call i32 @llvm.mips.lsa(i32 %a, i32 %b, i32 2) 15 ret i32 %0 16 } 17 18 declare i32 @llvm.mips.lsa(i32, i32, i32) nounwind 19 20 ; MIPS32: llvm_mips_lsa_test: 21 ; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2 22 ; MIPS32: .size llvm_mips_lsa_test 23 24 define i32 @lsa_test(i32 %a, i32 %b) nounwind { 25 entry: 26 %0 = shl i32 %b, 2 27 %1 = add i32 %a, %0 28 ret i32 %1 29 } 30 31 ; MIPS32: lsa_test: 32 ; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2 33 ; MIPS32: .size lsa_test 34 35 define i64 @llvm_mips_dlsa_test(i64 %a, i64 %b) nounwind { 36 entry: 37 %0 = tail call i64 @llvm.mips.dlsa(i64 %a, i64 %b, i32 2) 38 ret i64 %0 39 } 40 41 declare i64 @llvm.mips.dlsa(i64, i64, i32) nounwind 42 43 ; MIPS64: llvm_mips_dlsa_test: 44 ; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2 45 ; MIPS64: .size llvm_mips_dlsa_test 46 47 define i64 @dlsa_test(i64 %a, i64 %b) nounwind { 48 entry: 49 %0 = shl i64 %b, 2 50 %1 = add i64 %a, %0 51 ret i64 %1 52 } 53 54 ; MIPS64: dlsa_test: 55 ; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2 56 ; MIPS64: .size dlsa_test 57
