1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 2 ; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 3 4 ; FIXME: Enable for VI. 5 6 declare i32 @llvm.r600.read.tidig.x() nounwind readnone 7 declare void @llvm.AMDGPU.barrier.global() nounwind noduplicate 8 declare float @llvm.AMDGPU.div.fmas.f32(float, float, float, i1) nounwind readnone 9 declare double @llvm.AMDGPU.div.fmas.f64(double, double, double, i1) nounwind readnone 10 11 ; GCN-LABEL: {{^}}test_div_fmas_f32: 12 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb 13 ; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd 14 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc 15 ; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c 16 ; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34 17 ; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 18 ; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] 19 ; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] 20 ; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]] 21 ; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VB]], [[VA]], [[VC]] 22 ; GCN: buffer_store_dword [[RESULT]], 23 ; GCN: s_endpgm 24 define void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind { 25 %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone 26 store float %result, float addrspace(1)* %out, align 4 27 ret void 28 } 29 30 ; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_0: 31 ; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd 32 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc 33 ; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] 34 ; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] 35 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VB]], [[VC]] 36 ; SI: buffer_store_dword [[RESULT]], 37 ; SI: s_endpgm 38 define void @test_div_fmas_f32_inline_imm_0(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind { 39 %result = call float @llvm.AMDGPU.div.fmas.f32(float 1.0, float %b, float %c, i1 %d) nounwind readnone 40 store float %result, float addrspace(1)* %out, align 4 41 ret void 42 } 43 44 ; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_1: 45 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb 46 ; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd 47 ; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] 48 ; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]] 49 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VA]], [[VC]] 50 ; SI: buffer_store_dword [[RESULT]], 51 ; SI: s_endpgm 52 define void @test_div_fmas_f32_inline_imm_1(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind { 53 %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float 1.0, float %c, i1 %d) nounwind readnone 54 store float %result, float addrspace(1)* %out, align 4 55 ret void 56 } 57 58 ; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_2: 59 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb 60 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc 61 ; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]] 62 ; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] 63 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], 1.0 64 ; SI: buffer_store_dword [[RESULT]], 65 ; SI: s_endpgm 66 define void @test_div_fmas_f32_inline_imm_2(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind { 67 %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float 1.0, i1 %d) nounwind readnone 68 store float %result, float addrspace(1)* %out, align 4 69 ret void 70 } 71 72 ; GCN-LABEL: {{^}}test_div_fmas_f64: 73 ; GCN: v_div_fmas_f64 74 define void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind { 75 %result = call double @llvm.AMDGPU.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone 76 store double %result, double addrspace(1)* %out, align 8 77 ret void 78 } 79 80 ; GCN-LABEL: {{^}}test_div_fmas_f32_cond_to_vcc: 81 ; SI: v_cmp_eq_i32_e64 vcc, 0, s{{[0-9]+}} 82 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 83 define void @test_div_fmas_f32_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c, i32 %i) nounwind { 84 %cmp = icmp eq i32 %i, 0 85 %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %cmp) nounwind readnone 86 store float %result, float addrspace(1)* %out, align 4 87 ret void 88 } 89 90 ; GCN-LABEL: {{^}}test_div_fmas_f32_imm_false_cond_to_vcc: 91 ; SI: s_mov_b64 vcc, 0 92 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 93 define void @test_div_fmas_f32_imm_false_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { 94 %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 false) nounwind readnone 95 store float %result, float addrspace(1)* %out, align 4 96 ret void 97 } 98 99 ; GCN-LABEL: {{^}}test_div_fmas_f32_imm_true_cond_to_vcc: 100 ; SI: s_mov_b64 vcc, -1 101 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 102 define void @test_div_fmas_f32_imm_true_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { 103 %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 true) nounwind readnone 104 store float %result, float addrspace(1)* %out, align 4 105 ret void 106 } 107 108 ; GCN-LABEL: {{^}}test_div_fmas_f32_logical_cond_to_vcc: 109 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 110 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} 111 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} 112 113 ; SI-DAG: v_cmp_eq_i32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}} 114 ; SI-DAG: v_cmp_ne_i32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}} 115 ; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]] 116 ; SI: v_div_fmas_f32 {{v[0-9]+}}, [[A]], [[B]], [[C]] 117 ; SI: s_endpgm 118 define void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 %d) nounwind { 119 %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone 120 %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid 121 %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1 122 %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2 123 %gep.out = getelementptr float, float addrspace(1)* %out, i32 2 124 125 %a = load float, float addrspace(1)* %gep.a 126 %b = load float, float addrspace(1)* %gep.b 127 %c = load float, float addrspace(1)* %gep.c 128 129 %cmp0 = icmp eq i32 %tid, 0 130 %cmp1 = icmp ne i32 %d, 0 131 %and = and i1 %cmp0, %cmp1 132 133 %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %and) nounwind readnone 134 store float %result, float addrspace(1)* %gep.out, align 4 135 ret void 136 } 137 138 ; GCN-LABEL: {{^}}test_div_fmas_f32_i1_phi_vcc: 139 ; SI: v_cmp_eq_i32_e32 vcc, 0, v{{[0-9]+}} 140 ; SI: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc 141 ; SI: s_xor_b64 [[SAVE]], exec, [[SAVE]] 142 143 ; SI: buffer_load_dword [[LOAD:v[0-9]+]] 144 ; SI: v_cmp_ne_i32_e32 vcc, 0, [[LOAD]] 145 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc 146 147 148 ; SI: BB9_2: 149 ; SI: s_or_b64 exec, exec, [[SAVE]] 150 ; SI: v_cmp_ne_i32_e32 vcc, 0, v0 151 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 152 ; SI: buffer_store_dword 153 ; SI: s_endpgm 154 define void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 addrspace(1)* %dummy) nounwind { 155 entry: 156 %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone 157 %gep.out = getelementptr float, float addrspace(1)* %out, i32 2 158 %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid 159 %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1 160 %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2 161 162 %a = load float, float addrspace(1)* %gep.a 163 %b = load float, float addrspace(1)* %gep.b 164 %c = load float, float addrspace(1)* %gep.c 165 166 %cmp0 = icmp eq i32 %tid, 0 167 br i1 %cmp0, label %bb, label %exit 168 169 bb: 170 %val = load i32, i32 addrspace(1)* %dummy 171 %cmp1 = icmp ne i32 %val, 0 172 br label %exit 173 174 exit: 175 %cond = phi i1 [false, %entry], [%cmp1, %bb] 176 %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %cond) nounwind readnone 177 store float %result, float addrspace(1)* %gep.out, align 4 178 ret void 179 } 180
