1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s 2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s 3 4 ;CHECK-NOT: s_wqm 5 ;CHECK: s_mov_b32 6 ;CHECK-NEXT: v_interp_mov_f32 7 ;CHECK: v_interp_p1_f32 8 ;CHECK: v_interp_p2_f32 9 10 define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) #0 { 11 main_body: 12 %5 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3) 13 %6 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %4) 14 %7 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %4) 15 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %6, float %7, float %7) 16 ret void 17 } 18 19 declare void @llvm.AMDGPU.shader.type(i32) 20 21 ; Function Attrs: nounwind readnone 22 declare float @llvm.SI.fs.constant(i32, i32, i32) #1 23 24 ; Function Attrs: nounwind readnone 25 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 26 27 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) 28 29 attributes #0 = { "ShaderType"="0" } 30 attributes #1 = { nounwind readnone } 31
