1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC 2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC 3 ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC 4 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC 5 6 ; FUNC-LABEL: {{^}}u32_mad24: 7 ; EG: MULADD_UINT24 8 ; SI: v_mad_u32_u24 9 10 define void @u32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { 11 entry: 12 %0 = shl i32 %a, 8 13 %a_24 = lshr i32 %0, 8 14 %1 = shl i32 %b, 8 15 %b_24 = lshr i32 %1, 8 16 %2 = mul i32 %a_24, %b_24 17 %3 = add i32 %2, %c 18 store i32 %3, i32 addrspace(1)* %out 19 ret void 20 } 21 22 ; FUNC-LABEL: {{^}}i16_mad24: 23 ; The order of A and B does not matter. 24 ; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] 25 ; The result must be sign-extended 26 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x 27 ; EG: 16 28 ; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} 29 ; SI: v_bfe_i32 v{{[0-9]}}, [[MAD]], 0, 16 30 31 define void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) { 32 entry: 33 %0 = mul i16 %a, %b 34 %1 = add i16 %0, %c 35 %2 = sext i16 %1 to i32 36 store i32 %2, i32 addrspace(1)* %out 37 ret void 38 } 39 40 ; FUNC-LABEL: {{^}}i8_mad24: 41 ; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] 42 ; The result must be sign-extended 43 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x 44 ; EG: 8 45 ; SI: v_mad_u32_u24 [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}} 46 ; SI: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 8 47 48 define void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) { 49 entry: 50 %0 = mul i8 %a, %b 51 %1 = add i8 %0, %c 52 %2 = sext i8 %1 to i32 53 store i32 %2, i32 addrspace(1)* %out 54 ret void 55 } 56 57 ; This tests for a bug where the mad_u24 pattern matcher would call 58 ; SimplifyDemandedBits on the first operand of the mul instruction 59 ; assuming that the pattern would be matched to a 24-bit mad. This 60 ; led to some instructions being incorrectly erased when the entire 61 ; 24-bit mad pattern wasn't being matched. 62 63 ; Check that the select instruction is not deleted. 64 ; FUNC-LABEL: {{^}}i24_i32_i32_mad: 65 ; EG: CNDE_INT 66 ; SI: v_cndmask 67 define void @i24_i32_i32_mad(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) { 68 entry: 69 %0 = ashr i32 %a, 8 70 %1 = icmp ne i32 %c, 0 71 %2 = select i1 %1, i32 %0, i32 34 72 %3 = mul i32 %2, %c 73 %4 = add i32 %3, %d 74 store i32 %4, i32 addrspace(1)* %out 75 ret void 76 } 77
