1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s 2 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 3 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 4 5 ; FUNC-LABEL: {{^}}rotl_i32: 6 ; R600: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x 7 ; R600-NEXT: 32 8 ; R600: BIT_ALIGN_INT {{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].Z, PV.{{[XYZW]}} 9 10 ; SI: s_sub_i32 [[SDST:s[0-9]+]], 32, {{[s][0-9]+}} 11 ; SI: v_mov_b32_e32 [[VDST:v[0-9]+]], [[SDST]] 12 ; SI: v_alignbit_b32 {{v[0-9]+, [s][0-9]+, s[0-9]+}}, [[VDST]] 13 define void @rotl_i32(i32 addrspace(1)* %in, i32 %x, i32 %y) { 14 entry: 15 %0 = shl i32 %x, %y 16 %1 = sub i32 32, %y 17 %2 = lshr i32 %x, %1 18 %3 = or i32 %0, %2 19 store i32 %3, i32 addrspace(1)* %in 20 ret void 21 } 22 23 ; FUNC-LABEL: {{^}}rotl_v2i32: 24 ; SI-DAG: s_sub_i32 25 ; SI-DAG: s_sub_i32 26 ; SI-DAG: v_alignbit_b32 27 ; SI-DAG: v_alignbit_b32 28 ; SI: s_endpgm 29 define void @rotl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) { 30 entry: 31 %0 = shl <2 x i32> %x, %y 32 %1 = sub <2 x i32> <i32 32, i32 32>, %y 33 %2 = lshr <2 x i32> %x, %1 34 %3 = or <2 x i32> %0, %2 35 store <2 x i32> %3, <2 x i32> addrspace(1)* %in 36 ret void 37 } 38 39 ; FUNC-LABEL: {{^}}rotl_v4i32: 40 ; SI-DAG: s_sub_i32 41 ; SI-DAG: v_alignbit_b32 42 ; SI-DAG: s_sub_i32 43 ; SI-DAG: v_alignbit_b32 44 ; SI-DAG: s_sub_i32 45 ; SI-DAG: v_alignbit_b32 46 ; SI-DAG: s_sub_i32 47 ; SI-DAG: v_alignbit_b32 48 ; SI: s_endpgm 49 define void @rotl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) { 50 entry: 51 %0 = shl <4 x i32> %x, %y 52 %1 = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %y 53 %2 = lshr <4 x i32> %x, %1 54 %3 = or <4 x i32> %0, %2 55 store <4 x i32> %3, <4 x i32> addrspace(1)* %in 56 ret void 57 } 58
