1 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=dynamic-no-pic -disable-fp-elim | FileCheck %s 2 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC 3 ; rdar://7353541 4 ; rdar://7354376 5 6 @GV = external global i32 ; <i32*> [#uses=2] 7 8 define void @t1(i32* nocapture %vals, i32 %c) nounwind { 9 entry: 10 ; CHECK-LABEL: t1: 11 ; CHECK: bxeq lr 12 13 %0 = icmp eq i32 %c, 0 ; <i1> [#uses=1] 14 br i1 %0, label %return, label %bb.nph 15 16 bb.nph: ; preds = %entry 17 ; CHECK: movw r[[R2:[0-9]+]], :lower16:L_GV$non_lazy_ptr 18 ; CHECK: movt r[[R2]], :upper16:L_GV$non_lazy_ptr 19 ; CHECK: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]] 20 ; CHECK: ldr{{.*}}, [r[[R2b]] 21 ; CHECK: LBB0_ 22 ; CHECK-NOT: LCPI0_0: 23 24 ; PIC: movw r[[R2:[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4)) 25 ; PIC: movt r[[R2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4)) 26 ; PIC: add r[[R2]], pc 27 ; PIC: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]] 28 ; PIC: ldr{{.*}}, [r[[R2b]] 29 ; PIC: LBB0_ 30 ; PIC-NOT: LCPI0_0: 31 ; PIC: .section 32 %.pre = load i32, i32* @GV, align 4 ; <i32> [#uses=1] 33 br label %bb 34 35 bb: ; preds = %bb, %bb.nph 36 %1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; <i32> [#uses=1] 37 %i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; <i32> [#uses=2] 38 %scevgep = getelementptr i32, i32* %vals, i32 %i.03 ; <i32*> [#uses=1] 39 %2 = load i32, i32* %scevgep, align 4 ; <i32> [#uses=1] 40 %3 = add nsw i32 %1, %2 ; <i32> [#uses=2] 41 store i32 %3, i32* @GV, align 4 42 %4 = add i32 %i.03, 1 ; <i32> [#uses=2] 43 %exitcond = icmp eq i32 %4, %c ; <i1> [#uses=1] 44 br i1 %exitcond, label %return, label %bb 45 46 return: ; preds = %bb, %entry 47 ret void 48 } 49 50 ; rdar://8001136 51 define void @t2(i8* %ptr1, i8* %ptr2) nounwind { 52 entry: 53 ; CHECK-LABEL: t2: 54 ; CHECK: vmov.f32 q{{.*}}, #1.000000e+00 55 br i1 undef, label %bb1, label %bb2 56 57 bb1: 58 ; CHECK: %bb1 59 %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ] 60 %tmp1 = shl i32 %indvar, 2 61 %gep1 = getelementptr i8, i8* %ptr1, i32 %tmp1 62 %tmp2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %gep1, i32 1) 63 %tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <4 x float> %tmp2) 64 %gep2 = getelementptr i8, i8* %ptr2, i32 %tmp1 65 call void @llvm.arm.neon.vst1.v4f32(i8* %gep2, <4 x float> %tmp3, i32 1) 66 %indvar.next = add i32 %indvar, 1 67 %cond = icmp eq i32 %indvar.next, 10 68 br i1 %cond, label %bb2, label %bb1 69 70 bb2: 71 ret void 72 } 73 74 ; CHECK-NOT: LCPI1_0: 75 76 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly 77 78 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind 79 80 declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone 81 82 ; rdar://8241368 83 ; isel should not fold immediate into eor's which would have prevented LICM. 84 define zeroext i16 @t3(i8 zeroext %data, i16 zeroext %crc) nounwind readnone { 85 ; CHECK-LABEL: t3: 86 bb.nph: 87 ; CHECK: bb.nph 88 ; CHECK: movw {{(r[0-9])|(lr)}}, #32768 89 ; CHECK: movs {{(r[0-9]+)|(lr)}}, #0 90 ; CHECK: movw [[REGISTER:(r[0-9]+)|(lr)]], #16386 91 ; CHECK: movw {{(r[0-9]+)|(lr)}}, #65534 92 ; CHECK: movt {{(r[0-9]+)|(lr)}}, #65535 93 br label %bb 94 95 bb: ; preds = %bb, %bb.nph 96 ; CHECK: bb 97 ; CHECK: eor.w 98 ; CHECK: eorne.w {{(r[0-9])|(lr)}}, {{(r[0-9])|(lr)}}, [[REGISTER]] 99 ; CHECK-NOT: eor 100 ; CHECK: and 101 %data_addr.013 = phi i8 [ %data, %bb.nph ], [ %8, %bb ] ; <i8> [#uses=2] 102 %crc_addr.112 = phi i16 [ %crc, %bb.nph ], [ %crc_addr.2, %bb ] ; <i16> [#uses=3] 103 %i.011 = phi i8 [ 0, %bb.nph ], [ %7, %bb ] ; <i8> [#uses=1] 104 %0 = trunc i16 %crc_addr.112 to i8 ; <i8> [#uses=1] 105 %1 = xor i8 %data_addr.013, %0 ; <i8> [#uses=1] 106 %2 = and i8 %1, 1 ; <i8> [#uses=1] 107 %3 = icmp eq i8 %2, 0 ; <i1> [#uses=2] 108 %4 = xor i16 %crc_addr.112, 16386 ; <i16> [#uses=1] 109 %crc_addr.0 = select i1 %3, i16 %crc_addr.112, i16 %4 ; <i16> [#uses=1] 110 %5 = lshr i16 %crc_addr.0, 1 ; <i16> [#uses=2] 111 %6 = or i16 %5, -32768 ; <i16> [#uses=1] 112 %crc_addr.2 = select i1 %3, i16 %5, i16 %6 ; <i16> [#uses=2] 113 %7 = add i8 %i.011, 1 ; <i8> [#uses=2] 114 %8 = lshr i8 %data_addr.013, 1 ; <i8> [#uses=1] 115 %exitcond = icmp eq i8 %7, 8 ; <i1> [#uses=1] 116 br i1 %exitcond, label %bb8, label %bb 117 118 bb8: ; preds = %bb 119 ret i16 %crc_addr.2 120 } 121
