1 ; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s 2 3 ; These tests could be improved by 'movs r0, #0' being rematerialized below the 4 ; test as 'mov.w r0, #0'. 5 6 define i1 @f1(i32 %a, i32 %b) { 7 %nb = sub i32 0, %b 8 %tmp = icmp ne i32 %a, %nb 9 ret i1 %tmp 10 } 11 ; CHECK-LABEL: f1: 12 ; CHECK: cmn {{.*}}, r1 13 14 define i1 @f2(i32 %a, i32 %b) { 15 %nb = sub i32 0, %b 16 %tmp = icmp ne i32 %nb, %a 17 ret i1 %tmp 18 } 19 ; CHECK-LABEL: f2: 20 ; CHECK: cmn {{.*}}, r1 21 22 define i1 @f3(i32 %a, i32 %b) { 23 %nb = sub i32 0, %b 24 %tmp = icmp eq i32 %a, %nb 25 ret i1 %tmp 26 } 27 ; CHECK-LABEL: f3: 28 ; CHECK: cmn {{.*}}, r1 29 30 define i1 @f4(i32 %a, i32 %b) { 31 %nb = sub i32 0, %b 32 %tmp = icmp eq i32 %nb, %a 33 ret i1 %tmp 34 } 35 ; CHECK-LABEL: f4: 36 ; CHECK: cmn {{.*}}, r1 37 38 define i1 @f5(i32 %a, i32 %b) { 39 %tmp = shl i32 %b, 5 40 %nb = sub i32 0, %tmp 41 %tmp1 = icmp eq i32 %nb, %a 42 ret i1 %tmp1 43 } 44 ; CHECK-LABEL: f5: 45 ; CHECK: cmn.w {{.*}}, r1, lsl #5 46 47 define i1 @f6(i32 %a, i32 %b) { 48 %tmp = lshr i32 %b, 6 49 %nb = sub i32 0, %tmp 50 %tmp1 = icmp ne i32 %nb, %a 51 ret i1 %tmp1 52 } 53 ; CHECK-LABEL: f6: 54 ; CHECK: cmn.w {{.*}}, r1, lsr #6 55 56 define i1 @f7(i32 %a, i32 %b) { 57 %tmp = ashr i32 %b, 7 58 %nb = sub i32 0, %tmp 59 %tmp1 = icmp eq i32 %a, %nb 60 ret i1 %tmp1 61 } 62 ; CHECK-LABEL: f7: 63 ; CHECK: cmn.w {{.*}}, r1, asr #7 64 65 define i1 @f8(i32 %a, i32 %b) { 66 %l8 = shl i32 %a, 24 67 %r8 = lshr i32 %a, 8 68 %tmp = or i32 %l8, %r8 69 %nb = sub i32 0, %tmp 70 %tmp1 = icmp ne i32 %a, %nb 71 ret i1 %tmp1 72 } 73 ; CHECK-LABEL: f8: 74 ; CHECK: cmn.w {{.*}}, {{.*}}, ror #8 75 76 77 define void @f9(i32 %a, i32 %b) nounwind optsize { 78 tail call void asm sideeffect "cmn.w r0, r1", ""() nounwind, !srcloc !0 79 ret void 80 } 81 82 !0 = !{i32 81} 83 84 ; CHECK-LABEL: f9: 85 ; CHECK: cmn.w r0, r1 86
