1 ; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx -mattr=+avx 2 ; Various missing patterns causing crashes. 3 ; rdar://10538793 4 5 define void @t1() nounwind { 6 entry: 7 br label %loop.cond 8 9 loop.cond: ; preds = %t1.exit, %entry 10 br i1 false, label %return, label %loop 11 12 loop: ; preds = %loop.cond 13 br i1 undef, label %0, label %t1.exit 14 15 ; <label>:0 ; preds = %loop 16 %1 = load <16 x i32>, <16 x i32> addrspace(1)* undef, align 64 17 %2 = shufflevector <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> %1, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 0, i32 0> 18 store <16 x i32> %2, <16 x i32> addrspace(1)* undef, align 64 19 br label %t1.exit 20 21 t1.exit: ; preds = %0, %loop 22 br label %loop.cond 23 24 return: ; preds = %loop.cond 25 ret void 26 } 27 28 define void @t2() nounwind { 29 br i1 undef, label %1, label %4 30 31 ; <label>:1 ; preds = %0 32 %2 = load <16 x i32>, <16 x i32> addrspace(1)* undef, align 64 33 %3 = shufflevector <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> %2, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 20, i32 0, i32 0, i32 0, i32 0> 34 store <16 x i32> %3, <16 x i32> addrspace(1)* undef, align 64 35 br label %4 36 37 ; <label>:4 ; preds = %1, %0 38 ret void 39 } 40 41 define void @t3() nounwind { 42 entry: 43 br label %loop.cond 44 45 loop.cond: ; preds = %t2.exit, %entry 46 br i1 false, label %return, label %loop 47 48 loop: ; preds = %loop.cond 49 br i1 undef, label %0, label %t2.exit 50 51 ; <label>:0 ; preds = %loop 52 %1 = shufflevector <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> undef, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 25, i32 0> 53 %2 = load <16 x i32>, <16 x i32> addrspace(1)* undef, align 64 54 %3 = shufflevector <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> %2, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 28, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 55 store <16 x i32> %3, <16 x i32> addrspace(1)* undef, align 64 56 br label %t2.exit 57 58 t2.exit: ; preds = %0, %loop 59 br label %loop.cond 60 61 return: ; preds = %loop.cond 62 ret void 63 } 64 65 define <3 x i64> @t4() nounwind { 66 entry: 67 %0 = load <2 x i64>, <2 x i64> addrspace(1)* undef, align 16 68 %1 = extractelement <2 x i64> %0, i32 0 69 %2 = insertelement <3 x i64> <i64 undef, i64 0, i64 0>, i64 %1, i32 0 70 ret <3 x i64> %2 71 } 72 73 define void @t5() nounwind { 74 entry: 75 %0 = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 76 %1 = shufflevector <8 x i64> <i64 0, i64 0, i64 0, i64 undef, i64 undef, i64 0, i64 0, i64 0>, <8 x i64> %0, <8 x i32> <i32 0, i32 1, i32 2, i32 9, i32 8, i32 5, i32 6, i32 7> 77 store <8 x i64> %1, <8 x i64> addrspace(1)* undef, align 64 78 79 ret void 80 } 81
