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      1 ; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mtriple=x86_64-pc-win64 | FileCheck %s
      2 
      3 ; CHECK: merge_stores_can
      4 ; CHECK: callq foo
      5 ; CHECK: xorps %xmm0, %xmm0
      6 ; CHECK-NEXT: movups  %xmm0
      7 ; CHECK: callq foo
      8 ; CHECK: ret
      9 declare i32 @foo([10 x i32]* )
     10 
     11 define i32 @merge_stores_can() nounwind ssp {
     12   %object1 = alloca [10 x i32]
     13 
     14   %ret0 = call i32 @foo([10 x i32]* %object1) nounwind
     15 
     16   %O1_1 = getelementptr [10 x i32], [10 x i32]* %object1, i64 0, i32 1
     17   %O1_2 = getelementptr [10 x i32], [10 x i32]* %object1, i64 0, i32 2
     18   %O1_3 = getelementptr [10 x i32], [10 x i32]* %object1, i64 0, i32 3
     19   %O1_4 = getelementptr [10 x i32], [10 x i32]* %object1, i64 0, i32 4
     20   %ld_ptr = getelementptr [10 x i32], [10 x i32]* %object1, i64 0, i32 9
     21 
     22   store i32 0, i32* %O1_1
     23   store i32 0, i32* %O1_2
     24   %ret = load  i32,  i32* %ld_ptr  ; <--- does not alias.
     25   store i32 0, i32* %O1_3
     26   store i32 0, i32* %O1_4
     27 
     28   %ret1 = call i32 @foo([10 x i32]* %object1) nounwind
     29 
     30   ret i32 %ret
     31 }
     32 
     33 ; CHECK: merge_stores_cant
     34 ; CHECK-NOT: xorps %xmm0, %xmm0
     35 ; CHECK-NOT: movups  %xmm0
     36 ; CHECK: ret
     37 define i32 @merge_stores_cant([10 x i32]* %in0, [10 x i32]* %in1) nounwind ssp {
     38 
     39   %O1_1 = getelementptr [10 x i32], [10 x i32]* %in1, i64 0, i32 1
     40   %O1_2 = getelementptr [10 x i32], [10 x i32]* %in1, i64 0, i32 2
     41   %O1_3 = getelementptr [10 x i32], [10 x i32]* %in1, i64 0, i32 3
     42   %O1_4 = getelementptr [10 x i32], [10 x i32]* %in1, i64 0, i32 4
     43   %ld_ptr = getelementptr [10 x i32], [10 x i32]* %in0, i64 0, i32 2
     44 
     45   store i32 0, i32* %O1_1
     46   store i32 0, i32* %O1_2
     47   %ret = load  i32,  i32* %ld_ptr  ;  <--- may alias
     48   store i32 0, i32* %O1_3
     49   store i32 0, i32* %O1_4
     50 
     51   ret i32 %ret
     52 }
     53