1 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s 2 3 ; AVX2 Logical Shift Left 4 5 define <16 x i16> @test_sllw_1(<16 x i16> %InVec) { 6 entry: 7 %shl = shl <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 8 ret <16 x i16> %shl 9 } 10 11 ; CHECK-LABEL: test_sllw_1: 12 ; CHECK-NOT: vpsllw $0, %ymm0, %ymm0 13 ; CHECK: ret 14 15 define <16 x i16> @test_sllw_2(<16 x i16> %InVec) { 16 entry: 17 %shl = shl <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 18 ret <16 x i16> %shl 19 } 20 21 ; CHECK-LABEL: test_sllw_2: 22 ; CHECK: vpaddw %ymm0, %ymm0, %ymm0 23 ; CHECK: ret 24 25 define <16 x i16> @test_sllw_3(<16 x i16> %InVec) { 26 entry: 27 %shl = shl <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> 28 ret <16 x i16> %shl 29 } 30 31 ; CHECK-LABEL: test_sllw_3: 32 ; CHECK: vpsllw $15, %ymm0, %ymm0 33 ; CHECK: ret 34 35 define <8 x i32> @test_slld_1(<8 x i32> %InVec) { 36 entry: 37 %shl = shl <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 38 ret <8 x i32> %shl 39 } 40 41 ; CHECK-LABEL: test_slld_1: 42 ; CHECK-NOT: vpslld $0, %ymm0, %ymm0 43 ; CHECK: ret 44 45 define <8 x i32> @test_slld_2(<8 x i32> %InVec) { 46 entry: 47 %shl = shl <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> 48 ret <8 x i32> %shl 49 } 50 51 ; CHECK-LABEL: test_slld_2: 52 ; CHECK: vpaddd %ymm0, %ymm0, %ymm0 53 ; CHECK: ret 54 55 define <8 x i32> @test_vpslld_var(i32 %shift) { 56 %amt = insertelement <8 x i32> undef, i32 %shift, i32 0 57 %tmp = shl <8 x i32> <i32 192, i32 193, i32 194, i32 195, i32 196, i32 197, i32 198, i32 199>, %amt 58 ret <8 x i32> %tmp 59 } 60 61 ; CHECK-LABEL: test_vpslld_var: 62 ; CHECK: vpslld %xmm0, %ymm1, %ymm0 63 ; CHECK: ret 64 65 define <8 x i32> @test_slld_3(<8 x i32> %InVec) { 66 entry: 67 %shl = shl <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31> 68 ret <8 x i32> %shl 69 } 70 71 ; CHECK-LABEL: test_slld_3: 72 ; CHECK: vpslld $31, %ymm0, %ymm0 73 ; CHECK: ret 74 75 define <4 x i64> @test_sllq_1(<4 x i64> %InVec) { 76 entry: 77 %shl = shl <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0> 78 ret <4 x i64> %shl 79 } 80 81 ; CHECK-LABEL: test_sllq_1: 82 ; CHECK-NOT: vpsllq $0, %ymm0, %ymm0 83 ; CHECK: ret 84 85 define <4 x i64> @test_sllq_2(<4 x i64> %InVec) { 86 entry: 87 %shl = shl <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1> 88 ret <4 x i64> %shl 89 } 90 91 ; CHECK-LABEL: test_sllq_2: 92 ; CHECK: vpaddq %ymm0, %ymm0, %ymm0 93 ; CHECK: ret 94 95 define <4 x i64> @test_sllq_3(<4 x i64> %InVec) { 96 entry: 97 %shl = shl <4 x i64> %InVec, <i64 63, i64 63, i64 63, i64 63> 98 ret <4 x i64> %shl 99 } 100 101 ; CHECK-LABEL: test_sllq_3: 102 ; CHECK: vpsllq $63, %ymm0, %ymm0 103 ; CHECK: ret 104 105 ; AVX2 Arithmetic Shift 106 107 define <16 x i16> @test_sraw_1(<16 x i16> %InVec) { 108 entry: 109 %shl = ashr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 110 ret <16 x i16> %shl 111 } 112 113 ; CHECK-LABEL: test_sraw_1: 114 ; CHECK-NOT: vpsraw $0, %ymm0, %ymm0 115 ; CHECK: ret 116 117 define <16 x i16> @test_sraw_2(<16 x i16> %InVec) { 118 entry: 119 %shl = ashr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 120 ret <16 x i16> %shl 121 } 122 123 ; CHECK-LABEL: test_sraw_2: 124 ; CHECK: vpsraw $1, %ymm0, %ymm0 125 ; CHECK: ret 126 127 define <16 x i16> @test_sraw_3(<16 x i16> %InVec) { 128 entry: 129 %shl = ashr <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> 130 ret <16 x i16> %shl 131 } 132 133 ; CHECK-LABEL: test_sraw_3: 134 ; CHECK: vpsraw $15, %ymm0, %ymm0 135 ; CHECK: ret 136 137 define <8 x i32> @test_srad_1(<8 x i32> %InVec) { 138 entry: 139 %shl = ashr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 140 ret <8 x i32> %shl 141 } 142 143 ; CHECK-LABEL: test_srad_1: 144 ; CHECK-NOT: vpsrad $0, %ymm0, %ymm0 145 ; CHECK: ret 146 147 define <8 x i32> @test_srad_2(<8 x i32> %InVec) { 148 entry: 149 %shl = ashr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> 150 ret <8 x i32> %shl 151 } 152 153 ; CHECK-LABEL: test_srad_2: 154 ; CHECK: vpsrad $1, %ymm0, %ymm0 155 ; CHECK: ret 156 157 define <8 x i32> @test_srad_3(<8 x i32> %InVec) { 158 entry: 159 %shl = ashr <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31> 160 ret <8 x i32> %shl 161 } 162 163 ; CHECK-LABEL: test_srad_3: 164 ; CHECK: vpsrad $31, %ymm0, %ymm0 165 ; CHECK: ret 166 167 ; SSE Logical Shift Right 168 169 define <16 x i16> @test_srlw_1(<16 x i16> %InVec) { 170 entry: 171 %shl = lshr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 172 ret <16 x i16> %shl 173 } 174 175 ; CHECK-LABEL: test_srlw_1: 176 ; CHECK-NOT: vpsrlw $0, %ymm0, %ymm0 177 ; CHECK: ret 178 179 define <16 x i16> @test_srlw_2(<16 x i16> %InVec) { 180 entry: 181 %shl = lshr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 182 ret <16 x i16> %shl 183 } 184 185 ; CHECK-LABEL: test_srlw_2: 186 ; CHECK: vpsrlw $1, %ymm0, %ymm0 187 ; CHECK: ret 188 189 define <16 x i16> @test_srlw_3(<16 x i16> %InVec) { 190 entry: 191 %shl = lshr <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> 192 ret <16 x i16> %shl 193 } 194 195 ; CHECK-LABEL: test_srlw_3: 196 ; CHECK: vpsrlw $15, %ymm0, %ymm0 197 ; CHECK: ret 198 199 define <8 x i32> @test_srld_1(<8 x i32> %InVec) { 200 entry: 201 %shl = lshr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 202 ret <8 x i32> %shl 203 } 204 205 ; CHECK-LABEL: test_srld_1: 206 ; CHECK-NOT: vpsrld $0, %ymm0, %ymm0 207 ; CHECK: ret 208 209 define <8 x i32> @test_srld_2(<8 x i32> %InVec) { 210 entry: 211 %shl = lshr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> 212 ret <8 x i32> %shl 213 } 214 215 ; CHECK-LABEL: test_srld_2: 216 ; CHECK: vpsrld $1, %ymm0, %ymm0 217 ; CHECK: ret 218 219 define <8 x i32> @test_srld_3(<8 x i32> %InVec) { 220 entry: 221 %shl = lshr <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31> 222 ret <8 x i32> %shl 223 } 224 225 ; CHECK-LABEL: test_srld_3: 226 ; CHECK: vpsrld $31, %ymm0, %ymm0 227 ; CHECK: ret 228 229 define <4 x i64> @test_srlq_1(<4 x i64> %InVec) { 230 entry: 231 %shl = lshr <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0> 232 ret <4 x i64> %shl 233 } 234 235 ; CHECK-LABEL: test_srlq_1: 236 ; CHECK-NOT: vpsrlq $0, %ymm0, %ymm0 237 ; CHECK: ret 238 239 define <4 x i64> @test_srlq_2(<4 x i64> %InVec) { 240 entry: 241 %shl = lshr <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1> 242 ret <4 x i64> %shl 243 } 244 245 ; CHECK-LABEL: test_srlq_2: 246 ; CHECK: vpsrlq $1, %ymm0, %ymm0 247 ; CHECK: ret 248 249 define <4 x i64> @test_srlq_3(<4 x i64> %InVec) { 250 entry: 251 %shl = lshr <4 x i64> %InVec, <i64 63, i64 63, i64 63, i64 63> 252 ret <4 x i64> %shl 253 } 254 255 ; CHECK-LABEL: test_srlq_3: 256 ; CHECK: vpsrlq $63, %ymm0, %ymm0 257 ; CHECK: ret 258 259 ; CHECK-LABEL: @srl_trunc_and_v4i64 260 ; CHECK: vpand 261 ; CHECK-NEXT: vpsrlvd 262 ; CHECK: ret 263 define <4 x i32> @srl_trunc_and_v4i64(<4 x i32> %x, <4 x i64> %y) nounwind { 264 %and = and <4 x i64> %y, <i64 8, i64 8, i64 8, i64 8> 265 %trunc = trunc <4 x i64> %and to <4 x i32> 266 %sra = lshr <4 x i32> %x, %trunc 267 ret <4 x i32> %sra 268 } 269
