1 ; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck %s 2 3 4 define <4 x double> @test_x86_avx_blend_pd_256(<4 x double> %a0) { 5 %1 = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a0, i32 7) 6 ret <4 x double> %1 7 } 8 ; CHECK-LABEL: test_x86_avx_blend_pd_256 9 ; CHECK-NOT: vblendpd 10 ; CHECK: ret 11 12 13 define <8 x float> @test_x86_avx_blend_ps_256(<8 x float> %a0) { 14 %1 = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a0, i32 7) 15 ret <8 x float> %1 16 } 17 ; CHECK-LABEL: test_x86_avx_blend_ps_256 18 ; CHECK-NOT: vblendps 19 ; CHECK: ret 20 21 22 define <4 x double> @test_x86_avx_blendv_pd_256(<4 x double> %a0, <4 x double> %a1) { 23 %1 = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> %a0, <4 x double> %a0, <4 x double> %a1) 24 ret <4 x double> %1 25 } 26 ; CHECK-LABEL: test_x86_avx_blendv_pd_256 27 ; CHECK-NOT: vblendvpd 28 ; CHECK: ret 29 30 31 define <8 x float> @test_x86_avx_blendv_ps_256(<8 x float> %a0, <8 x float> %a1) { 32 %1 = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %a0, <8 x float> %a0, <8 x float> %a1) 33 ret <8 x float> %1 34 } 35 ; CHECK-LABEL: test_x86_avx_blendv_ps_256 36 ; CHECK-NOT: vblendvps 37 ; CHECK: ret 38 39 40 define <4 x double> @test2_x86_avx_blend_pd_256(<4 x double> %a0, <4 x double> %a1) { 41 %1 = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a1, i32 0) 42 ret <4 x double> %1 43 } 44 ; CHECK-LABEL: test2_x86_avx_blend_pd_256 45 ; CHECK-NOT: vblendpd 46 ; CHECK: ret 47 48 49 define <8 x float> @test2_x86_avx_blend_ps_256(<8 x float> %a0, <8 x float> %a1) { 50 %1 = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a1, i32 0) 51 ret <8 x float> %1 52 } 53 ; CHECK-LABEL: test2_x86_avx_blend_ps_256 54 ; CHECK-NOT: vblendps 55 ; CHECK: ret 56 57 58 define <4 x double> @test2_x86_avx_blendv_pd_256(<4 x double> %a0, <4 x double> %a1) { 59 %1 = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> zeroinitializer) 60 ret <4 x double> %1 61 } 62 ; CHECK-LABEL: test2_x86_avx_blendv_pd_256 63 ; CHECK-NOT: vblendvpd 64 ; CHECK: ret 65 66 67 define <8 x float> @test2_x86_avx_blendv_ps_256(<8 x float> %a0, <8 x float> %a1) { 68 %1 = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> zeroinitializer) 69 ret <8 x float> %1 70 } 71 ; CHECK-LABEL: test2_x86_avx_blendv_ps_256 72 ; CHECK-NOT: vblendvps 73 ; CHECK: ret 74 75 76 define <4 x double> @test3_x86_avx_blend_pd_256(<4 x double> %a0, <4 x double> %a1) { 77 %1 = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a1, i32 -1) 78 ret <4 x double> %1 79 } 80 ; CHECK-LABEL: test3_x86_avx_blend_pd_256 81 ; CHECK-NOT: vblendpd 82 ; CHECK: ret 83 84 85 define <8 x float> @test3_x86_avx_blend_ps_256(<8 x float> %a0, <8 x float> %a1) { 86 %1 = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a1, i32 -1) 87 ret <8 x float> %1 88 } 89 ; CHECK-LABEL: test3_x86_avx_blend_ps_256 90 ; CHECK-NOT: vblendps 91 ; CHECK: ret 92 93 94 define <4 x double> @test3_x86_avx_blendv_pd_256(<4 x double> %a0, <4 x double> %a1) { 95 %Mask = bitcast <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1> to <4 x double> 96 %1 = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %Mask) 97 ret <4 x double> %1 98 } 99 ; CHECK-LABEL: test3_x86_avx_blendv_pd_256 100 ; CHECK-NOT: vblendvpd 101 ; CHECK: ret 102 103 104 define <8 x float> @test3_x86_avx_blendv_ps_256(<8 x float> %a0, <8 x float> %a1) { 105 %Mask = bitcast <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1> to <8 x float> 106 %1 = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %Mask) 107 ret <8 x float> %1 108 } 109 ; CHECK-LABEL: test3_x86_avx_blendv_ps_256 110 ; CHECK-NOT: vblendvps 111 ; CHECK: ret 112 113 114 115 declare <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double>, <4 x double>, i32) 116 declare <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float>, <8 x float>, i32) 117 declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>) 118 declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>) 119 120
