1 ; RUN: llc -O0 -relocation-model=pic -disable-fp-elim < %s | FileCheck %s 2 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" 3 target triple = "x86_64-apple-darwin10" 4 5 ; This file contains functions that may crash llc -O0 6 7 ; The DIV8 instruction produces results in AH and AL, but we don't want to use 8 ; AH in 64-bit mode. The hack used must not generate copyFromReg nodes for 9 ; aliased registers (AX and AL) - RegAllocFast does not like that. 10 ; PR7312 11 define i32 @div8() nounwind { 12 entry: 13 %0 = trunc i64 undef to i8 ; <i8> [#uses=3] 14 %1 = udiv i8 0, %0 ; <i8> [#uses=1] 15 %2 = urem i8 0, %0 ; <i8> [#uses=1] 16 %3 = icmp uge i8 %2, %0 ; <i1> [#uses=1] 17 br i1 %3, label %"40", label %"39" 18 19 "39": ; preds = %"36" 20 %4 = zext i8 %1 to i32 ; <i32> [#uses=1] 21 %5 = mul nsw i32 %4, undef ; <i32> [#uses=1] 22 %6 = add nsw i32 %5, undef ; <i32> [#uses=1] 23 %7 = icmp ne i32 %6, undef ; <i1> [#uses=1] 24 br i1 %7, label %"40", label %"41" 25 26 "40": ; preds = %"39", %"36" 27 unreachable 28 29 "41": ; preds = %"39" 30 unreachable 31 } 32 33 ; When using fast isel, sdiv is lowered into a sequence of CQO + DIV64. 34 ; CQO defines implicitly AX and DIV64 uses it implicitly too. 35 ; When an instruction gets between those two, RegAllocFast was reusing 36 ; AX for the vreg defined in between and the compiler crashed. 37 ; 38 ; An instruction gets between CQO and DIV64 because the load is folded 39 ; into the division but it requires a sign extension. 40 ; PR21700 41 ; CHECK-LABEL: addressModeWith32bitIndex: 42 ; CHECK: cqto 43 ; CHECK-NEXT: movslq 44 ; CHECK-NEXT: idivq 45 ; CHECK: retq 46 define i64 @addressModeWith32bitIndex(i32 %V) { 47 %gep = getelementptr i64, i64* null, i32 %V 48 %load = load i64, i64* %gep 49 %sdiv = sdiv i64 0, %load 50 ret i64 %sdiv 51 } 52
