1 ; RUN: llc -march=x86 -mcpu=i486 -o - %s | FileCheck %s 2 3 ; Main test here was that ISelDAG could cope with a MachineNode in the chain 4 ; from the first load to the "X86ISD::SUB". Previously it thought that meant no 5 ; cycle could be formed so it tried to use "sub (%eax), [[RHS]]". 6 7 define void @gst_atomic_queue_push(i32* %addr) { 8 ; CHECK-LABEL: gst_atomic_queue_push: 9 ; CHECK: movl (%eax), [[LHS:%e[a-z]+]] 10 ; CHECK: lock 11 ; CHECK-NEXT: orl 12 ; CHECK: movl (%eax), [[RHS:%e[a-z]+]] 13 ; CHECK: cmpl [[LHS]], [[RHS]] 14 15 entry: 16 br label %while.body 17 18 while.body: 19 %0 = load volatile i32, i32* %addr, align 4 20 fence seq_cst 21 %1 = load volatile i32, i32* %addr, align 4 22 %cmp = icmp sgt i32 %1, %0 23 br i1 %cmp, label %while.body, label %if.then 24 25 if.then: 26 ret void 27 }
