1 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 > /dev/null 2 3 ; Verify that DAGCombiner doesn't crash with an assertion failure in the 4 ; attempt to cast a ISD::UNDEF node to a ConstantSDNode. 5 6 ; During type legalization, the vector shift operation in function @test1 is 7 ; split into two legal shifts that work on <2 x i64> elements. 8 ; The first shift of the legalized sequence would be a shift by all undefs. 9 ; DAGCombiner will then try to simplify the vector shift and check if the 10 ; vector of shift counts is a splat. Make sure that llc doesn't crash 11 ; at that stage. 12 13 14 define <4 x i64> @test1(<4 x i64> %A) { 15 %shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 1, i64 2> 16 ret <4 x i64> %shl 17 } 18 19 ; Also, verify that DAGCombiner doesn't crash when trying to combine shifts 20 ; with different combinations of undef elements in the vector shift count. 21 22 define <4 x i64> @test2(<4 x i64> %A) { 23 %shl = shl <4 x i64> %A, <i64 2, i64 3, i64 undef, i64 undef> 24 ret <4 x i64> %shl 25 } 26 27 define <4 x i64> @test3(<4 x i64> %A) { 28 %shl = shl <4 x i64> %A, <i64 2, i64 undef, i64 3, i64 undef> 29 ret <4 x i64> %shl 30 } 31 32 define <4 x i64> @test4(<4 x i64> %A) { 33 %shl = shl <4 x i64> %A, <i64 undef, i64 2, i64 undef, i64 3> 34 ret <4 x i64> %shl 35 } 36 37 define <4 x i64> @test5(<4 x i64> %A) { 38 %shl = shl <4 x i64> %A, <i64 2, i64 undef, i64 undef, i64 undef> 39 ret <4 x i64> %shl 40 } 41 42 define <4 x i64> @test6(<4 x i64> %A) { 43 %shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 3, i64 undef> 44 ret <4 x i64> %shl 45 } 46 47 define <4 x i64> @test7(<4 x i64> %A) { 48 %shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 undef, i64 3> 49 ret <4 x i64> %shl 50 } 51 52 define <4 x i64> @test8(<4 x i64> %A) { 53 %shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 undef, i64 undef> 54 ret <4 x i64> %shl 55 } 56 57 58
