1 ; RUN: llc < %s -verify-machineinstrs -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu -mcpu=nehalem -post-RA-scheduler=true -schedmodel=false | FileCheck %s 2 3 ; Currently, floating-point selects are lowered to CFG triangles. 4 ; This means that one side of the select is always unconditionally 5 ; evaluated, however with MachineSink we can sink the other side so 6 ; that it's conditionally evaluated. 7 8 ; CHECK-LABEL: foo: 9 ; CHECK-NEXT: testb $1, %dil 10 ; CHECK-NEXT: jne 11 ; CHECK-NEXT: divsd 12 ; CHECK-NEXT: movaps 13 ; CHECK-NEXT: ret 14 ; CHECK: divsd 15 16 define double @foo(double %x, double %y, i1 %c) nounwind { 17 %a = fdiv double %x, 3.2 18 %b = fdiv double %y, 3.3 19 %z = select i1 %c, double %a, double %b 20 ret double %z 21 } 22 23 ; Make sure the critical edge is broken so the divsd is sunken below 24 ; the conditional branch. 25 ; rdar://8454886 26 27 ; CHECK-LABEL: split: 28 ; CHECK-NEXT: testb $1, %dil 29 ; CHECK-NEXT: je 30 ; CHECK: divsd 31 ; CHECK: movaps 32 ; CHECK: ret 33 define double @split(double %x, double %y, i1 %c) nounwind { 34 %a = fdiv double %x, 3.2 35 %z = select i1 %c, double %a, double %y 36 ret double %z 37 } 38 39 40 ; Hoist floating-point constant-pool loads out of loops. 41 42 ; CHECK-LABEL: bar: 43 ; CHECK: movsd 44 ; CHECK: align 45 define void @bar(double* nocapture %p, i64 %n) nounwind { 46 entry: 47 %0 = icmp sgt i64 %n, 0 48 br i1 %0, label %bb, label %return 49 50 bb: 51 %i.03 = phi i64 [ 0, %entry ], [ %3, %bb ] 52 %scevgep = getelementptr double, double* %p, i64 %i.03 53 %1 = load double, double* %scevgep, align 8 54 %2 = fdiv double 3.200000e+00, %1 55 store double %2, double* %scevgep, align 8 56 %3 = add nsw i64 %i.03, 1 57 %exitcond = icmp eq i64 %3, %n 58 br i1 %exitcond, label %return, label %bb 59 60 return: 61 ret void 62 } 63 64 ; Sink instructions with dead EFLAGS defs. 65 66 ; FIXME: Unfail the zzz test if we can correctly mark pregs with the kill flag. 67 ; 68 ; See <rdar://problem/8030636>. This test isn't valid after we made machine 69 ; sinking more conservative about sinking instructions that define a preg into a 70 ; block when we don't know if the preg is killed within the current block. 71 72 73 ; FIXMEHECK: zzz: 74 ; FIXMEHECK: je 75 ; FIXMEHECK-NEXT: orb 76 77 ; define zeroext i8 @zzz(i8 zeroext %a, i8 zeroext %b) nounwind readnone { 78 ; entry: 79 ; %tmp = zext i8 %a to i32 ; <i32> [#uses=1] 80 ; %tmp2 = icmp eq i8 %a, 0 ; <i1> [#uses=1] 81 ; %tmp3 = or i8 %b, -128 ; <i8> [#uses=1] 82 ; %tmp4 = and i8 %b, 127 ; <i8> [#uses=1] 83 ; %b_addr.0 = select i1 %tmp2, i8 %tmp4, i8 %tmp3 ; <i8> [#uses=1] 84 ; ret i8 %b_addr.0 85 ; } 86 87 ; Codegen should hoist and CSE these constants. 88 89 ; CHECK-LABEL: vv: 90 ; CHECK: LCPI3_0(%rip), %xmm0 91 ; CHECK: LCPI3_1(%rip), %xmm1 92 ; CHECK: LCPI3_2(%rip), %xmm2 93 ; CHECK: align 94 ; CHECK-NOT: LCPI 95 ; CHECK: ret 96 97 @_minusZero.6007 = internal constant <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00> ; <<4 x float>*> [#uses=0] 98 @twoTo23.6008 = internal constant <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06> ; <<4 x float>*> [#uses=0] 99 100 define void @vv(float* %y, float* %x, i32* %n) nounwind ssp { 101 entry: 102 br label %bb60 103 104 bb: ; preds = %bb60 105 %i.0 = phi i32 [ 0, %bb60 ] ; <i32> [#uses=2] 106 %0 = bitcast float* %x_addr.0 to <4 x float>* ; <<4 x float>*> [#uses=1] 107 %1 = load <4 x float>, <4 x float>* %0, align 16 ; <<4 x float>> [#uses=4] 108 %tmp20 = bitcast <4 x float> %1 to <4 x i32> ; <<4 x i32>> [#uses=1] 109 %tmp22 = and <4 x i32> %tmp20, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> ; <<4 x i32>> [#uses=1] 110 %tmp23 = bitcast <4 x i32> %tmp22 to <4 x float> ; <<4 x float>> [#uses=1] 111 %tmp25 = bitcast <4 x float> %1 to <4 x i32> ; <<4 x i32>> [#uses=1] 112 %tmp27 = and <4 x i32> %tmp25, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> ; <<4 x i32>> [#uses=2] 113 %tmp30 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %tmp23, <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06>, i8 5) ; <<4 x float>> [#uses=1] 114 %tmp34 = bitcast <4 x float> %tmp30 to <4 x i32> ; <<4 x i32>> [#uses=1] 115 %tmp36 = xor <4 x i32> %tmp34, <i32 -1, i32 -1, i32 -1, i32 -1> ; <<4 x i32>> [#uses=1] 116 %tmp37 = and <4 x i32> %tmp36, <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200> ; <<4 x i32>> [#uses=1] 117 %tmp42 = or <4 x i32> %tmp37, %tmp27 ; <<4 x i32>> [#uses=1] 118 %tmp43 = bitcast <4 x i32> %tmp42 to <4 x float> ; <<4 x float>> [#uses=2] 119 %tmp45 = fadd <4 x float> %1, %tmp43 ; <<4 x float>> [#uses=1] 120 %tmp47 = fsub <4 x float> %tmp45, %tmp43 ; <<4 x float>> [#uses=2] 121 %tmp49 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %1, <4 x float> %tmp47, i8 1) ; <<4 x float>> [#uses=1] 122 %2 = bitcast <4 x float> %tmp49 to <4 x i32> ; <<4 x i32>> [#uses=1] 123 %3 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %2) nounwind readnone ; <<4 x float>> [#uses=1] 124 %tmp53 = fadd <4 x float> %tmp47, %3 ; <<4 x float>> [#uses=1] 125 %tmp55 = bitcast <4 x float> %tmp53 to <4 x i32> ; <<4 x i32>> [#uses=1] 126 %tmp57 = or <4 x i32> %tmp55, %tmp27 ; <<4 x i32>> [#uses=1] 127 %tmp58 = bitcast <4 x i32> %tmp57 to <4 x float> ; <<4 x float>> [#uses=1] 128 %4 = bitcast float* %y_addr.0 to <4 x float>* ; <<4 x float>*> [#uses=1] 129 store <4 x float> %tmp58, <4 x float>* %4, align 16 130 %5 = getelementptr float, float* %x_addr.0, i64 4 ; <float*> [#uses=1] 131 %6 = getelementptr float, float* %y_addr.0, i64 4 ; <float*> [#uses=1] 132 %7 = add i32 %i.0, 4 ; <i32> [#uses=1] 133 %8 = load i32, i32* %n, align 4 ; <i32> [#uses=1] 134 %9 = icmp sgt i32 %8, %7 ; <i1> [#uses=1] 135 br i1 %9, label %bb60, label %return 136 137 bb60: ; preds = %bb, %entry 138 %x_addr.0 = phi float* [ %x, %entry ], [ %5, %bb ] ; <float*> [#uses=2] 139 %y_addr.0 = phi float* [ %y, %entry ], [ %6, %bb ] ; <float*> [#uses=2] 140 br label %bb 141 142 return: ; preds = %bb60 143 ret void 144 } 145 146 declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone 147 148 declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone 149 150 ; CodeGen should use the correct register class when extracting 151 ; a load from a zero-extending load for hoisting. 152 153 ; CHECK-LABEL: default_get_pch_validity: 154 ; CHECK: movl cl_options_count(%rip), %ecx 155 156 @cl_options_count = external constant i32 ; <i32*> [#uses=2] 157 158 define void @default_get_pch_validity() nounwind { 159 entry: 160 %tmp4 = load i32, i32* @cl_options_count, align 4 ; <i32> [#uses=1] 161 %tmp5 = icmp eq i32 %tmp4, 0 ; <i1> [#uses=1] 162 br i1 %tmp5, label %bb6, label %bb2 163 164 bb2: ; preds = %bb2, %entry 165 %i.019 = phi i64 [ 0, %entry ], [ %tmp25, %bb2 ] ; <i64> [#uses=1] 166 %tmp25 = add i64 %i.019, 1 ; <i64> [#uses=2] 167 %tmp11 = load i32, i32* @cl_options_count, align 4 ; <i32> [#uses=1] 168 %tmp12 = zext i32 %tmp11 to i64 ; <i64> [#uses=1] 169 %tmp13 = icmp ugt i64 %tmp12, %tmp25 ; <i1> [#uses=1] 170 br i1 %tmp13, label %bb2, label %bb6 171 172 bb6: ; preds = %bb2, %entry 173 ret void 174 } 175
